ST STM8S

16-bit advanced control timer (TIM1) RM0016
144/449 Doc ID 14587 Rev 8
Figure 38. Counter update when ARPE = 0 (ARR not preloaded) with prescaler = 2
Figure 39. Counter update when ARPE = 1 (ARR preloaded), with prescaler = 1
CK_PSC
36
CNT_EN
TIMER CLOCK = CK_CNT
COUNTER REGISTER
UPDATE INTERRUPT FLAG (UIF)
COUNTER UNDERFLOW
UPDATE EVENT (UEV)
35 34 33 32 31 30 2F05 04 03 02 0106
AUTO-RELOAD PRELOAD REGISTER
FF 36
AUTO-RELOAD SHADOW REGISTER
Write a new value in TIMx_ARR
FF 36
New value transferred immediately in shadow register
00
FF
CNT_EN
TIMER CLOCK = CK_CNT
COUNTER REGISTER
UPDATE INTERRUPT FLAG (UIF)
COUNTER UNDERFLOW
UPDATE EVENT (UEV)
FE FD FC FB 36 35 3405 04 03 02 0106
AUTO-RELOAD PRELOAD REGISTER
FF 36
AUTO-RELOAD SHADOW REGISTER
FF 36
Write a new value in TIMx_ARR
CK_PSC
New value transferred in shadow register
on counter underflow
00
00
Cleared by software