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RM0016 16-bit advanced control timer (TIM1)

Doc ID 14587 Rev 8 199/449

17.7.11 Capture/compare mode register 3 (TIM1_CCMR3)

Address offset: 0x0A

Reset value: 0x00

Refer to the CCMR1 register description above.

Channel configured in output

Channel configured in input

76543210

OC3CE OC3M[2:0] OC3PE OC3FE CC3S[1:0]

rw rw rw rw rw rw rw rw

Bit 7 OC3CE: Output compare 3 clear enable

Bits 6:4 OC3M[2:0]: Output compare 3 mode

Bit 3 OC3PE: Output compare 3 preload enable

Bit 2 OC3FE: Output compare 3 fast enable

Bits 1:0 CC3S[1:0]: Capture/compare 3 selection

This bitfield defines the direction of the channel (input/output) and the used input.

00: CC3 channel is configured as output

01: CC3 channel is configured as input, IC3 is mapped on TI3FP3

10: CC3 channel is configured as input, IC3 is mapped on TI4FP3

11: Reserved

Note: CC3S bits are writable only when the channel is off (CC3E and CC3NE = 0 and updated in

TIM1_CCER2).

76543210

IC3F[3:0] IC3PSC[1:0] CC3S[1:0]

rw rw rw rw rw rw rw

Bits 7:4 IC3F: Input capture 3 filter

Bits 3:2 IC3PSC[1:0]: Input capture 3 prescaler