Serial peripheral interface (SPI) RM0016
268/449 Doc ID 14587 Rev 8
It is reset:
● when a transfer is finished (except in master mode if the communication is continuous)
● when the SPI is disabled
● when a master mode fault occurs (MODF = 1)
When communication is not continuous, the BSY flag is low between each communication.
When communication is continuous, in master mode, the BSY flag is kept high during the
whole transfers.
When communication is continuous, in slave mode, the BSY flag goes back to low state for
one SPI clock cycle between each transfer.
Note: Do not use the BSY flag to handle each data transmission or reception. It is better to use
TXE and RXNE flags instead.
20.3.8 Disabling the SPI
When a transfer is terminated, the application can stop the communication by disabling the
SPI peripheral. This is done by resetting the SPE bit.
For some configurations, disabling the SPI and entering Halt mode while a transfer is on-
going, can cause the current transfer to be corrupted and/or it can happen that the BSY flag
becomes unreliable.
To avoid any of these effects, it is recommended to respect the following procedure when
disabling the SPI:
In master or slave full duplex mode (BDM = 0, RXONLY = 0):
1. Wait until RXNE = 1 to receive the last data
2. Wait until TXE = 1
3. Then wait until BSY = 0
4. Disable the SPI (SPE = 0) and eventually enter Halt mode (or disable the peripheral
clock).
In master or slave unidirectional transmit-only mode (BDM = 0, RXONLY = 0)
or bidirectional transmit mode (BDM = 1, BDOE = 1):
After the last data is written in the SPI_DR register:
1. Wait until TXE = 1
2. Then wait until BSY = 0
3. Disable the SPI (SPE = 0) and, if desired, enter Halt mode (or disable the peripheral
clock).
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