8-bit basic timer (TIM4, TIM6) RM0016
250/449 Doc ID 14587 Rev 8
19.6.8 Prescaler register (TIMx_PSCR)
Address offset: 0x05 or 0x07 (TIM4), 0x07 (TIM6); for TIM4 address see Section 19.6.10
Reset value: 0x00
19.6.9 Auto-reload register (TIMx_ARR)
Address offset: 0x06 or 0x08 (TIM4), 0x08 (TIM6); for TIM4 address see Section 19.6.10
Reset value: 0xFF
76543210
Reserved
PSC[2:0]
rw
rw rw
Bits 7:3 Reserved, must be kept cleared
Bits 2:0 PSC[2:0]: Prescaler value
The prescaler value divides the CK_PSC clock frequency. The counter clock frequency f
CK_CNT
is
equal to f
CK_PSC
/ 2(PSC[2:0]).
PSC contains the value which is loaded into the active prescaler register at each UEV (including
when the counter is cleared through the UG bit of TIM4_EGR).
Consequently, a UEV must be generated so that a new prescaler value can be taken into account.
76543210
ARR[7:0]
rw rw rw rw rw
rw
rw rw
Bits 7:0 ARR[7:0]: Auto-reload value