Inter-integrated circuit (I
2
C) interface RM0016
298/449 Doc ID 14587 Rev 8
21.7.6 Data register (I2C_DR)
Address offset: 0x06
Reset value: 0x00
21.7.7 Status register 1 (I2C_SR1)
Address offset: 0x07
Reset value: 0x00
76543210
DR[7:0]
rw
Bits 7:0 DR[7:0]: Data register
(1)(2)(3)
Byte received or to be transmitted to the bus.
– Transmitter mode: Byte transmission starts automatically when a byte is written in the DR register. A
continuous transmit stream can be maintained if the next data to be transmitted is put in DR once
the transmission is started (TXE=1)
– Receiver mode: Received byte is copied into DR (RXNE=1). A continuous transmit stream can be
maintained if DR is read before the next data is received (RXNE=1).
1. In slave mode, the address is not copied into DR.
2. Write collision is not managed (DR can be written if TXE=0).
3. If an ARLO event occurs on ACK pulse, the received byte is not copied into DR and so cannot be read.
76543210
TXE RXNE
Reserved
STOPF ADD10 BTF ADDR SB
rr rrrrr
Bit 7 TXE: Data register empty (transmitters)
(1)
0: Data register not empty
1: Data register empty
– Set when DR is empty in transmission. TXE is not set during address phase.
– Cleared by software writing to the DR register or by hardware after a start or a stop condition or
when PE=0.
Note: TXE cannot be cleared by writing the first data in transmission or by writing a data when the
BTF bit is set as in both cases, the DR register is still empty.
Bit 6 RXNE: Data register not empty (receivers)
(2)
(3)
0: Data register empty
1: Data register not empty
– Set when data register is not empty in receiver mode. RXNE is not set during address phase.
– Cleared by software reading or writing the DR register or by hardware when PE=0.
Note: RXE cannot be cleared by reading a data when the BTF bit is set as the DR register is still full
in this case.
Bit 5 Reserved
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