Analog/digital converter (ADC) RM0016
422/449 Doc ID 14587 Rev 8
Table 75. ADC interrupts in scan mode (ADC1)
Control bits Status bits
Exit
from
Wait
Exit
from
Halt
AWENx
AWDIE
EOCIE
AWSx AWD EOC
0
Don’t
care
0 0 0
The flag is set at the end
of the scan sequence
No No
0
Don’t
care
1 0 0
The flag is set at the end
of the scan sequence
and an interrupt is
generated.
Ye s N o
1 0 0
Flag is set if conversion
on channel ”x” crosses
the thresholds
programmed in the
ADC_HTR and
ADC_LTR registers
The flag is set at the end
of the scan sequence if
at least one of the
AWSx bits is set
The flag is set at the end
of the scan sequence
No No
1 1 0
The flag is set and an
interrupt is generated at
the end of the SCAN
sequence if at least one
of the AWSx bits is set.
SCAN conversion is not
stopped.
The flag is set to 1 at the
end of the scan
sequence
Ye s N o
1 0 1
The flag is set at the end
of the scan sequence if
at least one of the
AWSx bits is set
The flag is set to 1 at the
end of the scan
sequence and an
interrupt is generated.
Ye s N o
1 1 1
The flag is set
immediately as soon as
one of the AWSx bits is
set. In interrupt is
generated and scan
conversion is stopped.
The flag is set at the end
of the scan sequence
and an interrupt is
generated.
Ye s N o