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16-bit general purpose timers (TIM2, TIM3, TIM5) RM0016

238/449 Doc ID 14587 Rev 8

18.6.19 Capture/compare register 1 low (TIMx_CCR1L)

Address offset: 00x10 or 0x12 (TIM2), 0x0E (TIM3), 0x12 (TIM5); for TIM2 address see

Section

Reset value: 0x00

18.6.20 Capture/compare register 2 high (TIMx_CCR2H)

Address offset: 00x11 or 0x13 (TIM2), 0x0F (TIM3), 0x13 (TIM5); for TIM2 address see

Section

Reset value: 0x00

18.6.21 Capture/compare register 2 low (TIMx_CCR2L)

Address offset: 00x12 or 0x14 (TIM2), 0x10 (TIM3), 0x14 (TIM5); for TIM2 address see

Section

Reset value: 0x00

76543210

CCR1[7:0]

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rw rw

Bits 7:0 CCR1[7:0]: Capture/compare 1 value (LSB)

76543210

CCR2[15:8]

rw rw rw rw rw rw rw rw

Bits 7:0 CCR2[15:8]: Capture/compare 2 value (MSB)

If the CC2 channel is configured as output (CC2S bits in TIMx_CCMR2 register):

The value of CCR2 is loaded permanently into the actual capture/compare 2 register if the preload

feature is not enabled (OC2PE bit in TIMx_CCMR2). Otherwise, the preload value is copied in the

active capture/compare 2 register when a UEV occurs. The active capture/compare register

contains the value which is compared to the counter register, TIMx_CNT, and signalled on the OC2

output.

If the CC2 channel is configured as input (CC2S bits in TIMx_CCMR2 register):

The value of CCR2 is the counter value transferred by the last input capture 2 event (IC2).

76543210

CCR2[7:0]

rw rw rw rw rw rw rw rw

Bits 7:0 CCR2[7:0]: Capture/compare value (LSB)

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