ST STM8S Reference Manual

RM0016 Inter-integrated circuit (I
2
C) interface
Doc ID 14587 Rev 8 291/449
Underrun error can occur in slave mode when clock stretching is disabled and the I2C
interface is transmitting data. The interface has not updated the DR with the next byte
(TXE=1), before the clock comes for the next byte. In this case,
● The same byte in the DR register will be sent again
● The user should make sure that data received on the receiver side during an underrun
error is discarded and that the next bytes are written within the clock low time specified
in the I
2
C bus standard.
● For the first byte to be transmitted, the DR must be written after ADDR is cleared and
before the first SCL rising edge. If it is not possible, the receiver must discard the first
data.
21.4.4 SDA/SCL line control
● If clock stretching is enabled:
– Transmitter mode: If TXE = 1 and BTF = 1: the interface holds the clock line low
before transmission to wait for the microcontroller to read SR1 and then write the
byte in the Data register (both buffer and shift register are empty).
– Receiver mode: If RXNE = 1 and BTF = 1: the interface holds the clock line low
after reception to wait for the microcontroller to read SR1 and then read the byte in
the Data Register or write to CR2 (both buffer and shift register are full).
● If clock stretching is disabled in Slave mode:
– Overrun error in case of RXNE = 1 and no read of DR has been done before the
next byte is received. The last received byte is lost.
– Underrun error in case TXE = 1 and no write into DR has been done before the
next byte must be transmitted. The same byte will be sent again.
– Write Collision not managed.
21.5 I
2
C low power modes
Table 48. I
2
C interface behavior in low power modes
Mode Description
Wait
No effect on I
2
C interface.
I
2
C interrupts cause the device to exit from Wait mode.
Halt
In slave mode: Communication is reset, except for configuration registers. Device is in
slave mode.
Wakeup from Halt interrupt is generated if ITEVTEN = 1 and address matched (including
allowed headers).
The matched address is not acknowledged in Halt mode so the master has to send it
again when the CPU is woken up to receive an acknowledge.
If NOSTRETCH = 0, SCLH will be stretched after acknowledge pulse in Halt mode until
WUFH is cleared by software;
None of the flags are set by the address which wakes up the CPU.
In master mode: Communication is frozen until the CPU is woken up. Wakeup from Halt
flag and interrupt are generated if ITEVTEN=1 and there is a HALT instruction.
Note: It is forbidden to enter Halt mode while a communication is on going.

ST STM8S Specifications

General

Brand	ST
Model	STM8S
Category	Microcontrollers
Language	English