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Universal async
hronous receiver transmit
ter (UART)
RM0016
360/449
Doc ID 14587 Re
v 8
22.7.13
U
ART register map and reset v
alues
T
able 61.
U
ART1 register map
Address
Regist
er
name
76543210
0x00
U
ART1_SR
Reset V
alue
TXE
1
TC
1
RXNE
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
0x01
UA
RT1_DR
Reset V
alue
DR7
x
DR6
x
DR5
x
DR4
x
DR3
x
DR2
x
DR1
x
DR0
x
0x02
UA
RT1_BRR1
Reset V
alue
U
ART_DIV[1
1:4]
00000000
0x03
UA
RT1_BRR2
Reset V
alue
U
ART_DIV[15:
12]
0000
U
ART_DIV
[3:0]
0000
0x04
UA
RT1_CR1
Reset V
alue
R8
0
T8
0
UA
RT
D
0
M
0
W
AKE
0
PCEN
0
PS
0
PIEN
0
0x05
UA
RT1_CR2
Reset V
alue
TIEN
0
TCIEN
0
RIEN
0
ILIEN
0
TEN
0
REN
0
RW
U
0
SBK
0
0x06
UA
RT1_CR3
Reset V
alue
-
0
LINEN
0
ST
OP
00
CKEN
0
CPOL
0
CPHA
0
LBCL
0
0x07
UA
RT1_CR4
Reset V
alue
-
0
LBDIEN
0
LBDL
0
LBDF
0
ADD[3:0]
0000
0x08
UA
RT1_CR5
Reset V
alue
-
0
-
0
SCEN
0
NACK
0
HDSEL
0
IRLP
0
IREN
00
0x09
UA
RT1_GTR
Reset V
alue
GT7
0
GT6
0
GT5
0
GT4
0
GT3
0
GT2
0
GT1
0
GT0
0
0x0A
UA
RT1_PSCR
Reset V
alue
PSC7
0
PSC6
0
PSC5
0
PSC4
0
PSC3
0
PSC2
0
PSC1
0
PSC0
0
T
able 62.
U
ART2 register map
Address
Regist
er
name
76543210
0x00
U
ART2_SR
Reset V
alue
TXE
1
TC
1
RXNE
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
0x01
UA
RT2_DR
Reset V
alue
DR7
x
DR6
x
DR5
x
DR4
x
DR3
x
DR2
x
DR1
x
DR0
x
0x02
UA
RT2_BRR1
Reset V
alue
U
ART_DIV[1
1:4]
00000000
0x03
UA
RT2_BRR2
Reset V
alue
U
ART_DIV[15:
12]
0000
U
ART_DIV
[3:0]
0000
0x04
UA
RT2_CR1
Reset V
alue
R8
0
T8
0
UA
RT
D
0
M
0
W
AKE
0
PCEN
0
PS
0
PIEN
0
0x05
UA
RT2_CR2
Reset V
alue
TIEN
0
TCIEN
0
RIEN
0
ILIEN
0
TEN
0
REN
0
RW
U
0
SBK
0
0x06
UA
RT2_CR3
Reset V
alue
-
0
LINEN
0
ST
OP
00
CKEN
0
CPOL
0
CPHA
0
LBCL
0
359
361
Table of Contents
Default Chapter
2
Table of Contents
2
Central Processing Unit (CPU)
23
Introduction
23
CPU Registers
23
Description of CPU Registers
23
Figure 1. Programming Model
24
Figure 2. Stacking Order
25
Table 1. Interrupt Levels
26
STM8 CPU Register Map
27
Global Configuration Register (CFG_GCR)
27
Activation Level
27
Table 2. CPU Register Map
27
SWIM Disable
28
Description of Global Configuration Register (CFG_GCR)
28
Global Configuration Register Map and Reset Values
28
Table 3. CFG_GCR Register Map
28
Boot ROM
29
Memory and Register Map
30
Memory Layout
30
Memory Map
30
Figure 3. Memory Map
30
Stack Handling
31
Figure 4. Default Stack Model
31
Figure 5. Customized Stack Model
32
Register Description Abbreviations
33
Table 4. List of Abbreviations
33
Flash Program Memory and Data EEPROM
34
Introduction
34
Glossary
34
Main Flash Memory Features
35
Memory Organization
36
STM8S and STM8A Memory Organization
36
Figure 6. Flash Memory and Data EEPROM Organization on Low Density STM8S
38
Figure 7. Flash Memory and Data EEPROM Organization on Medium Density STM8S and STM8A
39
Memory Access/ Wait State Configuration
40
User Boot Area (UBC)
40
Figure 8. Flash Memory and Data EEPROM Organization High Density STM8S and STM8A
40
Figure 9. UBC Area Size Definition on Low Density STM8S Devices
41
Figure 10. UBC Area Size Definition on Medium Density STM8S and STM8A with up to 32 Kbytes of Flash Program Memory
42
Data EEPROM (DATA)
43
Main Program Area
43
Option Bytes
43
Figure 11. UBC Area Size Definition on High Density STM8S and
43
Memory Protection
44
Readout Protection
44
Memory Access Security System (MASS)
44
Enabling Write Access to Option Bytes
46
Memory Programming
46
Read-While-Write (RWW)
46
Byte Programming
46
Word Programming
47
Block Programming
47
Option Byte Programming
49
ICP and IAP
49
Table 5. Block Size
49
Table 6. Memory Access Versus Programming Method
50
Flash Registers
51
Flash Control Register 1 (FLASH_CR1)
51
Flash Control Register 2 (FLASH_CR2)
52
Flash Complementary Control Register 2 (FLASH_NCR2)
53
Flash Protection Register (FLASH_FPR)
54
Flash Protection Register (FLASH_NFPR)
54
Flash Program Memory Unprotecting Key Register (FLASH_PUKR)
54
Data EEPROM Unprotection Key Register (FLASH_DUKR)
55
Flash Status Register (FLASH_IAPSR)
55
Flash Register Map and Reset Values
56
Table 7. Flash Register Map and Reset Values
56
Single Wire Interface Module (SWIM) and Debug Module (DM)
57
Introduction
57
Main Features
57
SWIM Modes
57
Figure 12. SWIM Pin Connection
57
Interrupt Controller (ITC)
58
ITC Introduction
58
Interrupt Masking and Processing Flow
58
Figure 13. Interrupt Processing Flowchart
59
Table 8. Software Priority Levels
59
Table 9. Interrupt Enabling/Disabling Inside an ISR
59
Figure 14. Priority Decision Process
60
Interrupt Sources
60
Servicing Pending Interrupts
60
Interrupts and Low Power Modes
62
Activation Level/Low Power Mode Control
62
Concurrent and Nested Interrupt Management
63
Concurrent Interrupt Management Mode
63
Figure 15. Concurrent Interrupt Management
63
Nested Interrupt Management Mode
64
Table 10. Vector Address Map Versus Software Priority Bits
64
External Interrupts
65
Interrupt Instructions
65
Table 11. Dedicated Interrupt Instruction Set
65
Figure 16. Nested Interrupt Management
65
Interrupt Mapping
66
ITC and EXTI Registers
67
CPU Condition Code Register Interrupt Bits (CCR)
67
Software Priority Register X (Itc_Sprx)
68
External Interrupt Control Register 1 (EXTI_CR1)
69
External Interrupt Control Register 1 (EXTI_CR2)
70
ITC and EXTI Register Map and Reset Values
71
Table 12. Interrupt Register Map
71
Power Supply
72
Figure 17. Power Supply Overview
72
Reset (RST)
73
Reset State" and "Under Reset" Definitions
73
Reset Circuit Description
73
Figure 18. Reset Circuit
73
Internal Reset Sources
74
Power-On Reset (POR) and Brown-Out Reset (BOR)
74
Figure 19. VDD/VDDIO Voltage Detection: POR/BOR Threshold
74
Watchdog Reset
75
Software Reset
75
SWIM Reset
75
Illegal Opcode Reset
75
EMC Reset
75
RST Register Description
76
Reset Status Register (RST_SR)
76
RST Register Map
76
Table 13. RST Register Map
76
Clock Control (CLK)
77
Figure 20. Clock Tree
78
Master Clock Sources
79
Hse
79
Figure 21. HSE Clock Sources
79
Hsi
80
Lsi
81
Table 14. Devices with 4 Trimming Bits
81
Table 15. Devices with 3 Trimming Bits
81
Master Clock Switching
82
System Startup
82
Master Clock Switching Procedures
82
Figure 22. Clock Switching Flowchart (Automatic Mode Example)
84
Low Speed Clock Selection
85
CPU Clock Divider
85
Figure 23. Clock Switching Flowchart (Manual Mode Example)
85
Peripheral Clock Gating (PCG)
86
Clock Security System (CSS)
87
Clock-Out Capability (CCO)
88
CLK Interrupts
88
Table 16. CLK Interrupt Requests
88
CLK Register Description
89
Internal Clock Register (CLK_ICKR)
89
External Clock Register (CLK_ECKR)
90
Clock Master Status Register (CLK_CMSR)
91
Clock Master Switch Register (CLK_SWR)
91
Switch Control Register (CLK_SWCR)
92
Clock Divider Register (CLK_CKDIVR)
93
Peripheral Clock Gating Register 1 (CLK_PCKENR1)
94
Table 17. Peripheral Clock Gating Bits
94
Peripheral Clock Gating Register 2 (CLK_PCKENR2)
95
Table 18. Peripheral Clock Gating Bits
95
Clock Security System Register (CLK_CSSR)
96
Configurable Clock Output Register (CLK_CCOR)
97
HSI Clock Calibration Trimming Register (CLK_HSITRIMR)
98
SWIM Clock Control Register (CLK_SWIMCCR)
99
CLK Register Map and Reset Values
100
Table 19. CLK Register Map and Reset Values
100
Power Management
101
General Considerations
101
Clock Management for Low Consumption
102
Low Power Modes
102
Table 20. Low Power Mode Management
102
Active-Halt Modes
103
Halt Mode
103
Wait Mode
103
Additional Analog Power Controls
104
Fast Flash Wakeup from Halt Mode
104
Very Low Flash Consumption in Active-Halt Mode
104
General Purpose I/O Ports (GPIO)
105
Introduction
105
GPIO Main Features
105
Port Configuration and Usage
106
Figure 24. GPIO Block Diagram
106
Input Modes
107
Output Modes
107
Table 21. I/O Port Configuration Summary
107
Reset Configuration
108
Unused I/O Pins
108
Low Power Modes
108
Input Mode Details
108
Alternate Function Input
108
Table 22. Effect of Low Power Modes on GPIO Ports
108
Interrupt Capability
109
Analog Channels
109
Schmitt Trigger
109
Output Mode Details
109
Alternate Function Output
109
Table 23. Recommended and Non-Recommended Configurations for Analog Input
109
Slope Control
110
GPIO Registers
111
Port X Output Data Register (Px_Odr)
111
Port X Pin Input Register (Px_Idr)
111
Port X Data Direction Register (Px_Ddr)
112
Port X Control Register 1 (Px_Cr1)
112
Port X Control Register 2 (Px_Cr2)
113
GPIO Register Map and Reset Values
113
Table 24. GPIO Register Map
113
Auto-Wakeup (AWU)
114
Introduction
114
LSI Clock Measurement
114
Figure 25. AWU Block Diagram
114
AWU Functional Description
115
AWU Operation
115
Time Base Selection
116
Table 25. Time Base Calculation Table
116
LSI Clock Frequency Measurement
117
AWU Registers
118
Control/Status Register (AWU_CSR)
118
Asynchronous Prescaler Register (AWU_APR)
118
Timebase Selection Register (AWU_TBR)
119
AWU Register Map and Reset Values
119
Table 26. AWU Register Map
119
Beeper (BEEP)
120
Introduction
120
Beeper Functional Description
120
Beeper Operation
120
Figure 26. Beep Block Diagram
120
Beeper Calibration
121
Beeper Registers
121
Beeper Control/Status Register (BEEP_CSR)
121
Beeper Register Map and Reset Values
121
Table 27. Beeper Register Map
121
Independent Watchdog (IWDG)
122
Introduction
122
IWDG Functional Description
122
Figure 27. Independent Watchdog (IWDG) Block Diagram
122
Table 28. Watchdog Timeout Period (LSI Clock Frequency = 128 Khz)
123
IWDG Registers
124
Key Register (IWDG_KR)
124
Prescaler Register (IWDG_PR)
124
Reload Register (IWDG_RLR)
125
IWDG Register Map and Reset Values
125
Table 29. IWDG Register Map
125
Window Watchdog (WWDG)
126
Introduction
126
WWDG Main Features
126
WWDG Functional Description
126
Figure 28. Watchdog Block Diagram
127
How to Program the Watchdog Timeout
128
Figure 29. Approximate Timeout Duration
128
WWDG Low Power Modes
129
Table 30. Window Watchdog Timing Example
129
Table 31. Effect of Low Power Modes on WWDG
129
Figure 30. Window Watchdog Timing Diagram
129
Hardware Watchdog Option
130
Using Halt Mode with the WWDG (WWDGHALT Option)
130
WWDG Interrupts
130
WWDG Registers
130
Control Register (WWDG_CR)
130
Window Register (WWDG_WR)
130
Window Watchdog Register Map and Reset Values
131
Table 32. WWDG Register Map and Reset Values
131
Timer Overview
132
Table 33. Timer Characteristics
132
Timer Feature Comparison
133
Glossary of Timer Signal Names
133
Table 34. Timer Feature Comparison
133
Table 35. Glossary of Internal Timer Signals
134
Figure 44: Control Circuit in Normal Mode, Fck_Psc = Fmaster
134
Table 36. Explanation of Indices'I', 'N', and 'X
135
16-Bit Advanced Control Timer (TIM1)
136
Introduction
136
TIM1 Main Features
137
Figure 31. TIM1 General Block Diagram
138
Figure 32. Time Base Unit
138
TIM1 Time Base Unit
139
Reading and Writing to the 16-Bit Counter
140
Write Sequence for 16-Bit TIM1_ARR Register
140
Prescaler
140
Figure 33. 16-Bit Read Sequence for the Counter (TIM1_CNTR)
140
Up-Counting Mode
141
Figure 34. Counter in Up-Counting Mode
141
Figure 35. Counter Update When ARPE = 0 (ARR Not Preloaded) with Prescaler = 2
142
Figure 36. Counter Update Event When ARPE = 1 (TIM1_ARR Preloaded)
142
Down-Counting Mode
143
Figure 37. Counter in Down-Counting Mode
143
Figure 38. Counter Update When ARPE = 0 (ARR Not Preloaded) with Prescaler = 2
144
Figure 39. Counter Update When ARPE = 1 (ARR Preloaded), with Prescaler = 1
144
Center-Aligned Mode (Up/Down Counting)
145
Figure 40. Counter in Center-Aligned Mode
145
Figure 41. Counter Timing Diagram, F CK_CNT = F CK_PSC , TIM1_ARR = 06H, ARPE = 1
146
Repetition Down-Counter
147
Figure 42. Update Rate Examples Depending on Mode and TIM1_RCR Register Settings
148
TIM1 Clock/Trigger Controller
149
Prescaler Clock (CK_PSC)
149
Figure 43. Clock/Trigger Controller Block Diagram
149
Internal Clock Source (Fmaster)
150
External Clock Source Mode 1
150
Figure 45. TI2 External Clock Connection Example
150
Figure 46. Control Circuit in External Clock Mode 1
151
External Clock Source Mode 2
152
Figure 47. External Trigger Input Block Diagram
152
Figure 48. Control Circuit in External Clock Mode 2
152
Trigger Synchronization
153
Figure 49. Control Circuit in Trigger Mode
153
Figure 50. Control Circuit in Trigger Reset Mode
154
Figure 51. Control Circuit in Trigger Gated Mode
155
Figure 52. Control Circuit in External Clock Mode 2 + Trigger Mode
156
Synchronization between TIM1, TIM5 and TIM6 Timers
157
Figure 53. Timer Chaining System Implementation Example
157
Figure 54. Trigger/Master Mode Selection Blocks
158
Figure 55. Master/Slave Timer Example
158
Figure 56. Gating Timer B with OC1REF of Timer a
159
Figure 57. Gating Timer B with the Counter Enable Signal of Timer a (CNT_EN)
160
Figure 58. Triggering Timer B with the UEV of Timer a (TIMERA-UEV)
161
Figure 59. Triggering Timer B with Counter Enable CNT_EN of Timer a
162
TIM1 Capture/Compare Channels
163
Figure 60. Triggering Timer a and B with Timer a TI1 Input
163
Figure 61. Capture/Compare Channel 1 Main Circuit
163
Figure 62. 16-Bit Read Sequence for the Tim1_Ccri Register in Capture Mode
164
Write Sequence for 16-Bit Tim1_Ccri Registers
164
Figure 63. Channel Input Stage Block Diagram
165
Figure 64. Input Stage of TIM 1 Channel 1
165
Input Stage
165
Input Capture Mode
166
Figure 65. PWM Input Signal Measurement
167
Figure 66. PWM Input Signal Measurement Example
168
Figure 67. Channel Output Stage Block Diagram
168
Output Stage
168
Figure 68. Detailed Output Stage of Channel with Complementary Output (Channel 1)
169
Forced Output Mode
169
Output Compare Mode
169
Figure 69. Output Compare Mode, Toggle on OC1
170
PWM Mode
171
Figure 70. Edge-Aligned Counting Mode PWM Mode 1 Waveforms (ARR = 8)
172
Figure 71. Center-Aligned PWM Waveforms (ARR = 8)
173
Figure 72. Example of One-Pulse Mode
174
Figure 73. Complementary Output with Deadtime Insertion
176
Figure 74. Deadtime Waveforms with a Delay Greater than the Negative Pulse
176
Figure 75. Deadtime Waveforms with a Delay Greater than the Positive Pulse
176
Figure 76. Six-Step Generation, COM Example (OSSR = 1)
178
Using the Break Function
178
Figure 77. Behavior of Outputs in Response to a Break (Channel Without Complementary Output)
179
Figure 78. Behavior of Outputs in Response to a Break (TIM1 Complementary Outputs)
180
Clearing the Ociref Signal on an External Event
181
Figure 79. ETR Activation
181
Encoder Interface Mode
182
Table 37. Counting Direction Versus Encoder Signals
182
Figure 80. Example of Counter Operation in Encoder Interface Mode
183
Figure 81. Example of Encoder Interface Mode with IC1 Polarity Inverted
183
TIM1 Interrupts
184
TIM1 Registers
185
Control Register 1 (TIM1_CR1)
185
Control Register 2 (TIM1_CR2)
187
Slave Mode Control Register (TIM1_SMCR)
188
External Trigger Register (TIM1_ETR)
189
Interrupt Enable Register (TIM1_IER)
191
Status Register 1 (TIM1_SR1)
192
Status Register 2 (TIM1_SR2)
193
Event Generation Register (TIM1_EGR)
194
Capture/Compare Mode Register 1 (TIM1_CCMR1)
195
Capture/Compare Mode Register 2 (TIM1_CCMR2)
198
Capture/Compare Mode Register 3 (TIM1_CCMR3)
199
Capture/Compare Mode Register 4 (TIM1_CCMR4)
200
Capture/Compare Enable Register 1 (TIM1_CCER1)
201
Table 38. Output Control for Complementary Oci and Ocin Channels with Break Feature
202
Capture/Compare Enable Register 2 (TIM1_CCER2)
204
Counter High (TIM1_CNTRH)
204
Counter Low (TIM1_CNTRL)
205
Prescaler High (TIM1_PSCRH)
205
Prescaler Low (TIM1_PSCRL)
205
Auto-Reload Register High (TIM1_ARRH)
206
Auto-Reload Register Low (TIM1_ARRL)
206
Repetition Counter Register (TIM1_RCR)
206
Capture/Compare Register 1 High (TIM1_CCR1H)
207
Capture/Compare Register 1 Low (TIM1_CCR1L)
207
Capture/Compare Register 2 High (TIM1_CCR2H)
208
Capture/Compare Register 2 Low (TIM1_CCR2L)
208
Capture/Compare Register 3 High (TIM1_CCR3H)
209
Capture/Compare Register 3 Low (TIM1_CCR3L)
209
Capture/Compare Register 4 High (TIM1_CCR4H)
210
Capture/Compare Register 4 Low (TIM1_CCR4L)
210
Break Register (TIM1_BKR)
211
Deadtime Register (TIM1_DTR)
212
Output Idle State Register (TIM1_OISR)
213
TIM1 Register Map and Reset Values
214
Table 39. TIM1 Register Map
214
16-Bit General Purpose Timers (TIM2, TIM3, TIM5)
216
Introduction
216
TIM2/TIM3 Main Features
216
TIM5 Main Features
217
TIM2/TIM3/TIM5 Functional Description
217
Figure 82. TIM2/TIM3 Block Diagram
217
Figure 84. Time Base Unit
217
Figure 83. TIM5 Block Diagram
218
Time Base Unit
218
Clock/Trigger Controller
219
Capture/Compare Channels
220
Figure 85. Input Stage Block Diagram
220
Figure 86. Input Stage of TIM 2 Channel 1
220
TIM2/TIM3/TIM5 Interrupts
221
Figure 87. Output Stage
221
Figure 88. Output Stage of Channel 1
221
TIM2/TIM3/TIM5 Registers
223
Control Register 1 (Timx_Cr1)
223
Control Register 2 (TIM5_CR2)
224
Slave Mode Control Register (TIM5_SMCR)
225
Interrupt Enable Register (Timx_Ier)
226
Status Register 1 (Timx_Sr1)
227
Status Register 2 (Timx_Sr2)
228
Event Generation Register (Timx_Egr)
229
Capture/Compare Mode Register 1 (Timx_Ccmr1)
230
Capture/Compare Mode Register 2 (Timx_Ccmr2)
232
Capture/Compare Mode Register 3 (Timx_Ccmr3)
233
Capture/Compare Enable Register 1 (Timx_Ccer1)
234
Capture/Compare Enable Register 2 (Timx_Ccer2)
235
Counter High (Timx_Cntrh)
235
Counter Low (Timx_Cntrl)
236
Prescaler Register (Timx_Pscr)
236
Auto-Reload Register High (Timx_Arrh)
236
Auto-Reload Register Low (Timx_Arrl)
237
Capture/Compare Register 1 High (Timx_Ccr1H)
237
Capture/Compare Register 1 Low (Timx_Ccr1L)
238
Capture/Compare Register 2 High (Timx_Ccr2H)
238
Capture/Compare Register 2 Low (Timx_Ccr2L)
238
Capture/Compare Register 3 High (Timx_Ccr3H)
239
Capture/Compare Register 3 Low (Timx_Ccr3L)
239
Table 40. TIM2 Register Map
239
Table 41. TIM3 Register Map
241
Table 42. TIM5 Register Map
241
8-Bit Basic Timer (TIM4, TIM6)
243
Introduction
243
Figure 89. TIM4 Block Diagram
243
Figure 90. TIM6 Block Diagram
243
TIM4 Main Features
244
TIM6 Main Features
244
TIM4/TIM6 Interrupts
244
TIM4/TIM6 Clock Selection
244
TIM4/TIM6 Registers
245
Control Register 1 (Timx_Cr1)
245
Control Register 2 (TIM6_CR2)
246
Slave Mode Control Register (TIM6_SMCR)
246
Interrupt Enable Register (Timx_Ier)
247
Status Register 1 (Timx_Sr)
248
Event Generation Register (Timx_Egr)
248
Counter (Timx_Cntr)
249
Prescaler Register (Timx_Pscr)
250
Auto-Reload Register (Timx_Arr)
250
TIM4/TIM6 Register Map and Reset Values
251
Table 43. TIM4 Register Map
251
Table 44. TIM6 Register Map
251
Serial Peripheral Interface (SPI)
253
Introduction
253
SPI Main Features
253
SPI Functional Description
254
General Description
254
Figure 91. SPI Block Diagram
254
Figure 92. Single Master/ Single Slave Application
255
Figure 93. Data Clock Timing Diagram
257
Configuring the SPI in Slave Mode
258
Configuring the SPI Master Mode
258
Configuring the SPI for Simplex Communications
259
Data Transmission and Reception Procedures
259
Figure 94. TXE/RXNE/BSY Behavior in Full Duplex Mode (RXONLY = 0). Case of Continuous Transfers
262
Figure 95. TXE/RXNE/BSY Behavior in Slave / Full Duplex Mode
262
Figure 96. TXE/BSY in Master Transmit-Only Mode
263
Figure 97. TXE/BSY in Slave Transmit-Only Mode (BDM = 0 and RXONLY = 0)
264
Figure 98. RXNE Behavior in Receive-Only Mode (BDM = 0 and RXONLY = 1)
265
CRC Calculation
266
Figure 99. TXE/BSY Behavior When Transmitting (BDM = 0 and RXLONY = 0). Case of Discontinuous Transfers
266
Status Flags
267
Disabling the SPI
268
Error Flags
269
SPI Low Power Modes
270
Table 45. SPI Behavior in Low Power Modes
270
SPI Interrupts
271
SPI Registers
271
SPI Control Register 1 (SPI_CR1)
271
Table 46. SPI Interrupt Requests
271
SPI Control Register 2 (SPI_CR2)
272
SPI Interrupt Control Register (SPI_ICR)
274
SPI Status Register (SPI_SR)
275
SPI Data Register (SPI_DR)
276
SPI CRC Polynomial Register (SPI_CRCPR)
276
SPI Rx CRC Register (SPI_RXCRCR)
276
SPI Tx CRC Register (SPI_TXCRCR)
277
SPI Register Map and Reset Values
277
Table 47. SPI Register Map and Reset Values
277
Inter-Integrated Circuit (I 2 C) Interface
278
Introduction
278
I 2 C Main Features
278
C General Description
279
Figure 100. I 2 C Bus Protocol
279
I 2 C Functional Description
281
I 2 C Slave Mode
281
Figure 102. Transfer Sequence Diagram for Slave Transmitter
282
I 2 C Master Mode
283
Figure 103. Transfer Sequence Diagram for Slave Receiver
283
Figure 104. Transfer Sequence Diagram for Master Transmitter
285
Figure 105. Method 1: Transfer Sequence Diagram for Master Receiver
286
Figure 106. Method 2: Transfer Sequence Diagram for Master Receiver When N >2
287
Figure 107. Method 2: Transfer Sequence Diagram for Master Receiver When N=2
288
Error Conditions
289
Figure 108. Method 2: Transfer Sequence Diagram for Master Receiver When N=1
289
SDA/SCL Line Control
291
I 2 C Low Power Modes
291
Table 48. I 2 C Interface Behavior in Low Power Modes
291
I 2 C Interrupts
292
Table 49. I 2 C Interrupt Requests
292
Figure 109. I2C Interrupt Mapping Diagram
292
I 2 C Registers
293
Control Register 1 (I2C_CR1)
293
Control Register 2 (I2C_CR2)
294
Frequency Register (I2C_FREQR)
296
Own Address Register LSB (I2C_OARL)
297
Own Address Register MSB (I2C_OARH)
297
Data Register (I2C_DR)
298
Status Register 1 (I2C_SR1)
298
Status Register 2 (I2C_SR2)
300
Status Register 3 (I2C_SR3)
301
Interrupt Register (I2C_ITR)
302
Clock Control Register Low (I2C_CCRL)
303
Clock Control Register High (I2C_CCRH)
304
TRISE Register (I2C_TRISER)
305
Table 50. I2C_CCR Values for SCL Frequency Table (Fmaster = 10 Mhz or 16 Mhz)
305
C Register Map and Reset Values
306
Table 51. I 2 C Register Map
306
Universal Asynchronous Receiver Transmitter (UART)
307
Introduction
307
Table 52. UART Configurations
307
UART Main Features
308
UART Functional Description
309
Figure 110. UART1 Block Diagram
310
Figure 111. UART2 Block Diagram
311
Figure 112. UART3 Block Diagram
312
Figure 113. Word Length Programming
313
UART Character Description
313
Transmitter
314
Figure 114. Configurable Stop Bits
315
Figure 115. TC/TXE Behavior When Transmitting
316
Figure 116. Start Bit Detection
317
Receiver
317
Figure 117. Data Sampling for Noise Detection
319
Table 53. Noise Detection from Sampled Data
320
Figure 118. How to Code UART_DIV in the BRR Registers
321
High Precision Baud Rate Generator
321
Clock Deviation Tolerance of the UART Receiver
322
Table 54. Baud Rate Programming and Error Calculation
322
Table 55. UART Receiver Tolerance When UART_DIV[3:0] Is Zero
322
Parity Control
323
Table 56. UART Receiver's Tolerance When UART_DIV[3:0] Is Different from Zero
323
Table 57. Frame Format
323
Figure 119. Mute Mode Using Idle Line Detection
324
Multi-Processor Communication
324
Figure 120. Mute Mode Using Address Mark Detection
325
LIN (Local Interconnection Network) Mode
325
UART Synchronous Communication
326
Figure 121. UART Example of Synchronous Transmission
327
Figure 122. UART Data Clock Timing Diagram (M=0)
327
Figure 123. UART Data Clock Timing Diagram (M=1)
327
Figure 124. RX Data Setup/Hold Time
328
Single Wire Half Duplex Communication
328
Smartcard
328
Figure 125. ISO 7816-3 Asynchronous Protocol
329
Figure 126. Parity Error Detection Using 1.5 Stop Bits
330
Irda SIR ENDEC Block
330
Figure 127. Irda SIR ENDEC- Block Diagram
332
Figure 128. Irda Data Modulation (3/16) - Normal Mode
332
LIN Mode Functional Description
333
Master Mode
333
Figure 129. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)
335
Figure 130. Break Detection in LIN Mode Vs Framing Error Detection
336
Slave Mode with Automatic Resynchronization Disabled
337
Figure 131. LIN Identifier Field Parity Bits
338
Figure 132. LIN Identifier Field Parity Check
338
Figure 133. LIN Header Reception Time-Out
339
Slave Mode with Automatic Resynchronization Enabled
340
Figure 134. LIN Synch Field Measurement
341
Figure 135. UARTDIV Read / Write Operations When LDUM = 0
341
Figure 136. UARTDIV Read / Write Operations When LDUM = 1
342
LIN Mode Selection
345
Table 58. LIN Mode Selection
345
Figure 137. Bit Sampling in Reception Mode
345
UART Low Power Modes
346
UART Interrupts
346
Table 59. UART Interface Behavior in Low Power Modes
346
Table 60. UART Interrupt Requests
346
Figure 138. UART Interrupt Mapping Diagram
347
UART Registers
348
Status Register (UART_SR)
348
Data Register (UART_DR)
350
Baud Rate Register 1 (UART_BRR1)
350
Baud Rate Register 2 (UART_BRR2)
351
Control Register 1 (UART_CR1)
351
Control Register 2 (UART_CR2)
352
Control Register 3 (UART_CR3)
354
Control Register 4 (UART_CR4)
355
Control Register 5 (UART_CR5)
356
Control Register 6 (UART_CR6)
357
Guard Time Register (UART_GTR)
358
Prescaler Register (UART_PSCR)
359
UART Register Map and Reset Values
360
Table 61. UART1 Register Map
360
Table 62. UART2 Register Map
360
Table 63. UART3 Register Map
361
Controller Area Network (Becan)
362
Introduction
362
Becan Main Features
362
Becan General Description
363
CAN 2.0B Active Core
363
Control, Status and Configuration Registers
363
Figure 139. CAN Network Topology
363
Tx Mailboxes
364
Acceptance Filters
364
Figure 140. Becan Block Diagram
364
Operating Modes
365
Initialization Mode
365
Figure 141. Becan Operating Modes
365
Normal Mode
366
Sleep Mode (Low Power)
366
Time Triggered Communication Mode
366
Test Modes
367
Silent Mode
367
Loop Back Mode
367
Figure 142. Becan in Silent Mode
367
Figure 143. Becan in Loop Back Mode
367
Loop Back Combined with Silent Mode
368
Functional Description
368
Transmission Handling
368
Figure 144. Becan in Combined Mode
368
Figure 145. Transmit Mailbox States
370
Reception Handling
371
Figure 146. Receive FIFO States
371
Identifier Filtering
372
Figure 147. 32-Bit Filter Bank Configuration (Fscx Bits = 0B11 in Can_Fcrx Register)
374
Figure 148. 16-Bit Filter Bank Configuration (Fscx Bits = 0B10 in Can_Fcrx Register)
374
Figure 149. 16/8-Bit Filter Bank Configuration (Fscx Bits = 0B01 in Can_Fcrx Register)
375
Figure 150. 8-Bit Filter Bank Configuration (Fscx Bits = 0B00 in Can_Fcrx Register)
375
Table 64. Example of Filter Numbering
376
Figure 151. Filter Banks Configured as in the Example in
377
Message Storage
378
Table 65. Transmit Mailbox Mapping
378
Table 66. Receive Mailbox Mapping
379
Error Management
380
Figure 152. CAN Error State Diagram
380
Bit Timing
381
Figure 153. Bit Timing
381
Figure 154. CAN Frames
382
Interrupts
383
Figure 155. Event Flags and Interrupt Generation
383
Register Access Protection
384
Clock System
384
Becan Low Power Modes
384
Table 67. Becan Behavior in Low Power Modes
384
Becan Registers
385
CAN Master Control Register (CAN_MCR)
385
CAN Master Status Register (CAN_MSR)
386
CAN Transmit Status Register (CAN_TSR)
387
CAN Transmit Priority Register (CAN_TPR)
388
CAN Receive FIFO Register (CAN_RFR)
389
CAN Interrupt Enable Register (CAN_IER)
390
CAN Diagnostic Register (CAN_DGR)
391
CAN Page Select Register (CAN_PSR)
391
CAN Error Status Register (CAN_ESR)
392
CAN Error Interrupt Enable Register (CAN_EIER)
393
CAN Transmit Error Counter Register (CAN_TECR)
393
CAN Receive Error Counter Register (CAN_RECR)
394
CAN Bit Timing Register 1 (CAN_BTR1)
394
CAN Bit Timing Register 2 (CAN_BTR2)
395
23.11.15 Mailbox Registers
396
23.11.16 CAN Filter Registers
401
CAN Register Map
407
Figure 156. CAN Register Mapping
407
Figure 157. CAN Page Mapping
408
Page Mapping for CAN
408
Table 68. Becan Control and Status Page - Register Map and Reset Values
409
Table 69. Becan Mailbox Pages - Register Map and Reset Values
409
Table 70. Becan Filter Configuration Page - Register Map and Reset Values
410
Analog/Digital Converter (ADC)
411
Introduction
411
ADC Main Features
411
ADC Extended Features
411
Figure 158. ADC1 Block Diagram
412
Figure 159. ADC2 Block Diagram
413
ADC Pins
414
ADC Functional Description
414
ADC On-Off Control
414
ADC Clock
414
Channel Selection
415
Conversion Modes
415
Overrun Flag
416
Analog Watchdog
417
Figure 160. Analog Watchdog Guarded Area
417
Conversion on External Trigger
418
Analog Zooming
418
Timing Diagram
418
Figure 161. Timing Diagram in Single Mode (CONT = 0)
419
Figure 162. Timing Diagram in Continuous Mode (CONT = 1)
419
ADC Low Power Modes
420
ADC Interrupts
420
Table 72. Low Power Modes
420
Table 73. ADC Interrupts in Single and Non-Buffered Continuous Mode (ADC1 and ADC2)
420
Table 74. ADC Interrupts in Buffered Continuous Mode (ADC1)
421
Table 75. ADC Interrupts in Scan Mode (ADC1)
422
Data Alignment
423
Reading the Conversion Result
423
Figure 163. Right Alignment of Data
423
Figure 164. Left Alignment of Data
423
Schmitt Trigger Disable Registers
424
ADC Registers
425
ADC Data Buffer Register X High (Adc_Dbxrh) (X=0..7 or 0..9
425
ADC Data Buffer Register X Low (Adc_Dbxrl) (X=Or 0
426
ADC Control/Status Register (ADC_CSR)
427
ADC Configuration Register 1 (ADC_CR1)
428
ADC Configuration Register 2 (ADC_CR2)
429
ADC Configuration Register 3 (ADC_CR3)
430
ADC Data Register High (ADC_DRH)
431
ADC Data Register Low (ADC_DRL)
431
ADC Schmitt Trigger Disable Register High (ADC_TDRH)
432
ADC Schmitt Trigger Disable Register Low (ADC_TDRL)
432
ADC High Threshold Register High (ADC_HTRH)
433
ADC High Threshold Register Low (ADC_HTRL)
433
ADC Low Threshold Register High (ADC_LTRH)
434
ADC Low Threshold Register Low (ADC_LTRL)
434
ADC Watchdog Status Register High (ADC_AWSRH)
435
ADC Watchdog Status Register Low (ADC_AWSRL)
435
ADC Watchdog Control Register High (ADC_AWCRH)
436
Table 76. ADC1 Register Map and Reset Values
437
Table 77. ADC2 Register Map and Reset Values
438
Revision History
439
Table 78. Document Revision History
440
Figure 101. I 2 C Block Diagram
444
Other manuals for ST STM8S
User Manual
23 pages
Application Note
42 pages
Getting Started
40 pages
5
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ST STM8S Specifications
General
Brand
ST
Model
STM8S
Category
Microcontrollers
Language
English
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