RM0016 16-bit general purpose timers (TIM2, TIM3, TIM5)
Doc ID 14587 Rev 8 219/449
For more details refer to Section 17.3: TIM1 time base unit on page 139.
Prescaler
The prescaler implementation is as follows:
● The prescaler is based on a 16-bit counter controlled through a 4-bit register (in the
TIMx_PSCR register). It can be changed on the fly as this control register is buffered. It
can divide the counter clock frequency by any power of 2 from 1 to 32768.
The counter clock frequency is calculated as follows:
f
CK_CNT
= f
CK_PSC
/2
(PSCR[3:0])
The prescaler value is loaded through a preload register. The shadow register, which
contains the current value to be used is loaded as soon as the LS Byte has been written.
The new prescaler value is taken into account in the following period (after the next counter
update event).
Read operations to the TIMx_PSCR registers access the preload registers, so no special
care needs to be taken to read them.
Counter operation
Refer to Section 17.3.4: Up-counting mode on page 141.
18.4.2 Clock/trigger controller
A clock/trigger controller and the associated TIMx_CR2 and TIMx_SMCR registers are not
implemented in TIM2/TIM3, only in TIM5. Refer to Section 17.4: TIM1 clock/trigger controller
on page 149
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