Universal asynchronous receiver transmitter (UART) RM0016
348/449 Doc ID 14587 Rev 8
22.7 UART registers
22.7.1 Status register (UART_SR)
Address offset: 0x00
Reset value: 0xC0
76543210
TXE TC RXNE IDLE OR/LHE NF FE PE
rrc_w0rc_w0rrrrr
Bit 7 TXE: Transmit data register empty
This bit is set by hardware when the content of the TDR register has been transferred into the shift
register. An interrupt is generated if the TIEN bit =1 in the UART_CR2 register. It is cleared by a
write to the UART_DR register.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 6 TC: Transmission complete
This bit is set by hardware if the transmission of a frame containing data is complete and TXE bit is
set. An interrupt is generated if TCIEN=1 in the UART_CR2 register. The TC bit is cleared either by
a software sequence (a read to the UART_SR register followed by a write to the UART_DR register),
or by programming the bit to ‘0’. This clear sequence is recommended only for multibuffer
communications.
0: Transmission is not complete
1: Transmission is complete
Bit 5 RXNE: Read data register not empty
This bit is set by hardware when the content of the RDR shift register has been transferred to the
UART_DR register. An interrupt is generated if RIEN=1 in the UART_CR2 register. It is cleared by a
read to the UART_DR register. In UART2 and UART3, it can also be cleared by writing 0.
0: Data is not received
1: Received data is ready to be read.
Bit 4 IDLE: IDLE line detected
(1)
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the ILIEN=1 in
the UART_CR2 register. It is cleared by a software sequence (a read to the UART_SR register
followed by a read to the UART_DR register).
0: No Idle Line is detected
1: Idle Line is detected
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