RM0016 Controller area network (beCAN)
Doc ID 14587 Rev 8 389/449
23.11.5 CAN receive FIFO register (CAN_RFR)
Address offset: 0x04
Reset value: 0x00
76543210
Reserved
RFOM FOVR FULL
Reserved
FMP[1:0]
rs rc_w1 rc_w1 r r
Bit 7:6 Reserved.
Bit 5 RFOM Release FIFO Output Mailbox
Set by software to release the output mailbox of the FIFO. The output mailbox can only be released
when at least one message is pending in the FIFO. Setting this bit when the FIFO is empty has no
effect. If more than one message is pending in the FIFO, the software has to release the output
mailbox to access the next message.
Cleared by hardware when the output mailbox has been released.
Bit 4 FOVR FIFO Overrun
This bit is set by hardware when a new message has been received and passed the filter while the
FIFO was full.
This bit is cleared by software writing ‘1’.
Bit 3 FULL FIFO Full
Set by hardware when three messages are stored in the FIFO.
This bit can be cleared by software writing ‘1’ or by releasing the FIFO by means of RFOM.
Bit 2 Reserved.
Bits 1:0 FMP[1:0] FIFO Message Pending
These bits indicate how many messages are pending in the receive FIFO.
FMP is increased each time the hardware stores a new message in to the FIFO. FMP is decreased
each time the FIFO output mailbox has been released by hardware (RFOM bit has been cleared
after prior setting by software).
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