ST STM8S Reference Manual

RM0016 Clock control (CLK)
Doc ID 14587 Rev 8 97/449
9.9.10 Configurable clock output register (CLK_CCOR)
Address offset: 0x09
Reset value: 0x00
76543210
Reserved
CCOBSY CCORDY CCOSEL[3:0] CCOEN
r r rw rw rw rw rw
Bit 7 Reserved, must be kept cleared.
Bit 6 CCOBSY: Configurable clock output busy
This bit is set and cleared by hardware. It indicates that the selected CCO clock source is being
switched-on and stabilized. While CCOBSY is set, the CCOSEL bits are write-protected. CCOBSY
remains set until the CCO clock is enabled.
0: CCO clock not busy
1: CCO clock busy
Bit 5 CCORDY: Configurable clock output ready
This bit is set and cleared by hardware. It indicates that the CCO clock is being output.
0: CCO clock not available
1: CCO clock available
Bits 4:1 CCOSEL[3:0]: Configurable clock output selection.
These bits are written by software to select the source of the output clock available on the CLK_CCO
pin. They are write-protected when CCOBSY is set.
0000: f
HSIDIV
0001: f
LSI
0010: f
HSE
0011: Reserved
0100: f
CPU
0101: f
CPU
/2
0110: f
CPU
/4
0111: f
CPU
/8
1000: f
CPU
/16
1001: f
CPU
/32
1010: f
CPU
/64
1011: f
HSI
1100: f
MASTER
1101: f
CPU
1110: f
CPU
1111: f
CPU
Bit 0 CCOEN: Configurable clock output enable
This bit is set and cleared by software.
0: CCO clock output disabled
1: CCO clock output enabled

ST STM8S Specifications

General

Brand	ST
Model	STM8S
Category	Microcontrollers
Language	English