Central processing unit (CPU) RM0016
26/449 Doc ID 14587 Rev 8
● H: Half carry bit
The H bit is set to 1 when a carry occurs between the bits 3 and 4 of the ALU during an ADD
or ADC instruction. The H bit is useful in BCD arithmetic subroutines.
● I0: Interrupt mask level 0
See Flag I1.
● N: Negative
When set to 1, this bit indicates that the result of the last arithmetic, logical or data
manipulation is negative (i.e. the most significant bit is a logic 1).
● Z: Zero
When set to 1, this bit indicates that the result of the last arithmetic, logical or data
manipulation is zero.
● C: Carry
When set, C indicates that a carry or borrow out of the ALU occurred during the last
arithmetic operation on the MSB operation result bit. This bit is also affected during bit test,
branch, shift, rotate and load instructions. See the ADD, ADC, SUB, and SBC instructions.
In a division operation, C indicates if trouble occurred during execution (quotient overflow or
zero division). See the DIV instruction.
In bit test operations, C is the copy of the tested bit. See the BTJF and BTJT instructions.
In shift and rotate operations, the carry is updated. See the RRC, RLC, SRL, SLL, and SRA
instructions.
This bit can be set, reset or complemented by software using the SCF, RCF, and CCF
instructions.
Table 1. Interrupt levels
Interruptability Priority I1 I0
Interruptable main
Lowest
Highest
10
Interruptable level 1 0 1
Interruptable level 2 0 0
Non interruptable 1 1
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