Reset (RST) RM0016
74/449 Doc ID 14587 Rev 8
An internal temporization maintains a pulse of duration t
OP(NRST)
whatever the internal reset
source. An additional internal weak pull-up ensures a high level on the reset pin when the
reset is not forced.
8.3 Internal reset sources
Each internal reset source is linked to a specific flag bit in the Reset status register
(RST_SR) except POR/BOR which have no flag. These flags are set respectively at reset
depending on the given reset source. So they are used to identify the last reset source. They
are cleared by software writing the logic value “1”.
8.3.1 Power-on reset (POR) and brown-out reset (BOR)
During power-on, the POR keeps the device under reset until the supply voltages (V
DD and
V
DDIO
) reach the voltage level at which the BOR starts to function. At this point, the BOR
reset replaces the POR and the POR is automatically switched off. The BOR reset is
maintained till the supply voltage reaches the operating voltage range.
See Electrical parameters section of the datasheet for more details.
The BOR also generates a reset when the supply voltage drops below the V
IT-
threshold.
When this occurs, the POR is re-armed for the next power-on phase.
An hysteresis is implemented to ensure clean detection of voltage rise and fall.
The BOR always remains active even when the MCU is put into Low Power mode.
Figure 19. V
DD/
V
DDIO
voltage detection: POR/BOR threshold
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