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RM0016 8-bit basic timer (TIM4, TIM6)

Doc ID 14587 Rev 8 245/449

19.6 TIM4/TIM6 registers

19.6.1 Control register 1 (TIMx_CR1)

Address offset: 0x00

Reset value: 0x00

76543210

ARPE

Reserved

OPM URS UDIS CEN

rw rw rw rw rw

Bit 7 ARPE: Auto-reload preload enable

0: TIM4_ARR register is not buffered through a preload register. It can be written directly

1: TIM4_ARR register is buffered through a preload register

Bits 6:4 Reserved, must be kept cleared

Bit 3 OPM: One-pulse mode

0: Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the CEN bit)

Bit 2 URS: Update request source

0: When enabled, an update interrupt request is sent as soon as registers are updated (counter

overflow).

1: When enabled, an update interrupt request is sent only when the counter reaches the

overflow/underflow.

Bit 1 UDIS: Update disable

0: A UEV is generated as soon as a counter overflow occurs or a software update is generated.

Buffered registers are then loaded with their preload values.

1: A UEV is not generated, shadow registers keep their value (ARR, PSC). The counter and the

prescaler are re-initialized if the UG bit is set.

Bit 0 CEN: Counter enable

0: Counter disable

1: Counter enable

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