ST STM8S

RM0016 Inter-integrated circuit (I
2
C) interface
Doc ID 14587 Rev 8 303/449
21.7.11 Clock control register low (I2C_CCRL)
Address offset: 0x02
Reset value: 0x0B
76543210
CCR[7:0]
rw
Bits 7:0 CCR[7:0] Clock control register (Master mode)
Controls the SCLH clock in Master mode.
– Standard mode:
Period(I2C) = 2 * CCR * t
MASTER
t
high
= CCR * t
MASTER
t
low
= CCR * t
MASTER
– Fast mode:
If DUTY = 0:
Period(I2C) = 3* CCR * t
MASTER
t
high
= CCR * t
MASTER
t
low
= 2 * CCR * t
MASTER
If DUTY = 1: (to reach 400 kHz)
Period(I2C) = 25 * CCR * t
MASTER
t
high
= 9 * CCR * t
MASTER
t
low
= 16 * CCR * t
MASTER
Note: t
CK
= 1/ f
MASTER
. f
MASTER
is the input clock to the peripheral configured using clock control
register.
The minimum allowed value is 04h, except in FAST DUTY mode where the minimum allowed
value is 0x01.
t
high
= t
r(SCL)
+ t
w(SCLH)
. See device datasheet for the definitions of parameters.
t
low
= t
f(SCL)
+ t
w(SCLL)
. See device datasheet for the definitions of parameters.
I2C communication speed, f
SCL
= 1/(t
high
+ t
low
)
These timings are without filters.