ST STM8S - CaptureCompare Register 3 High (TIM1 CCR3 H); CaptureCompare Register 3 Low (TIM1 CCR3 L)

RM0016 16-bit advanced control timer (TIM1)
Doc ID 14587 Rev 8 209/449
17.7.26 Capture/compare register 3 high (TIM1_CCR3H)
Address offset: 0x19
Reset value: 0x00
17.7.27 Capture/compare register 3 low (TIM1_CCR3L)
Address offset: 0x1A
Reset value: 0x00
76543210
CCR3[15:8]
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Bits 7:0 CCR3[15:8]: Capture/compare value (MSB)
If the CC3 channel is configured as output (CC3S bits in TIM1_CCMR3 register):
The value of CCR3 is loaded permanently into the actual capture/compare 3 register if the preload
feature is not enabled (OC3PE bit in TIM1_CCMR3). Otherwise, the preload value is copied in the
active capture/compare 3 register when a UEV occurs.The active capture/compare register contains
the value which is compared to the counter register, TIM1_CNT, and signalled on the OC3 output.
If the CC3 channel is configured as input (CC3S bits in TIM1_CCMR3 register):
The value of CCR3 is the counter value transferred by the last input capture 3 event (IC31).
76543210
CCR3[7:0]
rw rw rw rw rw rw rw rw
Bits 7:0 CCR3[7:0]: Capture/compare value (LSB)