RM0016 8-bit basic timer (TIM4, TIM6)
Doc ID 14587 Rev 8 247/449
19.6.4 Interrupt enable register (TIMx_IER)
Address offset: 0x01 or 0x03 (TIM4), 0x03 (TIM6); for TIM4 address see Section 19.6.10
Reset value: 0x00
Bits 6:4 TS[2:0]: Trigger selection
This bitfield selects the trigger input to be used to synchronize the counter.
000: Reserved
001: reserved
010: Internal trigger ITR2 connected to TIM5 TRGO
011: Internal trigger ITR3 connected to TIM1 TRGO
100: Reserved
101: Reserved
110: Reserved
111: Reserved
Note: These bits must only be changed when they are not used (e.g. when SMS = 000) to avoid
wrong edge detections at the transition.
Bit 3 Reserved.
Bits 2:0 SMS[2:0]:Clock/trigger/slave mode selection
When external signals are selected, the active edge of the trigger signal (TRGI) is linked to the
polarity selected on the external input (see Input control register and control register description).
000: Clock/trigger controller disabled - If CEN = 1, the prescaler is clocked directly by the internal
clock.
001: Reserved
010: Reserved
011: Reserved
100: Trigger reset mode - The rising edge of the selected trigger signal (TRGI) reinitializes the
counter and generates an update of the registers.
101: Gated mode - The counter clock is enabled when the trigger signal (TRGI) is high. The counter
stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are
controlled.
110: Trigger mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only
the start of the counter is controlled.
111: External clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
76543210
Reserved
TIE
Reserved
UIE
rw rw
Bit 7 Reserved, must be kept cleared
Bit 6 TIE: Trigger interrupt enable
0: Trigger Interrupt disabled
1: Trigger Interrupt enabled
Note: In TIM4 this bit is reserved.
Bits 5:1 Reserved, must be kept cleared
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled
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