ST STM8S

RM0016 Auto-wakeup (AWU)
Doc ID 14587 Rev 8 119/449
12.4.3 Timebase selection register (AWU_TBR)
Address offset: 0x02
Reset value: 0x00
12.4.4 AWU register map and reset values
76543210
Reserved
AWUTB[3:0]
rw
Bits 7:4 Reserved
Bits 3:0 AWUTB[3:0]: Auto-wakeup timebase selection
These bits are written by software to define the time interval between AWU interrupts. AWU
interrupts are enabled when AWUEN = 1.
0000: No interrupt
0001: APR
DIV
/f
LS
0010: 2xAPR
DIV
/f
LS
0011: 2
2
APR
DIV
/f
LS
0100: 2
3
APR
DIV
/f
LS
0101: 2
4
APR
DIV
/f
LS
0110: 2
5
APR
DIV
/f
LS
0111: 2
6
APR
DIV
/f
LS
1000: 2
7
APR
DIV
/f
LS
1001: 2
8
APR
DIV
/f
LS
1010: 2
9
APR
DIV
/f
LS
1011: 2
10
APR
DIV
/f
LS
1100: 2
11
APR
DIV
/f
LS
1101: 2
12
APR
DIV
/f
LS
1110: 5x2
11
APR
DIV
/f
LS
1111: 30x2
11
APR
DIV
/f
LS
Table 26. AWU register map
Address
offset
Register
name
7654 3 2 1 0
0x00 AWU_CSR
-
0
-
0
AWUF
0
AWUEN
0
-
0
-
0
-
0
MSR
0
0x01 AWU_APR
-
0
-
0
APR5
1
APR4
1
APR3
1
APR2
1
APR1
1
APR0
1
0x02 AWU_TBR
-
0
-
0
-
0
-
0
AWUTB3
0
AWUTB2
0
AWUTB1
0
AWUTB0
0