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ST STM8S Reference Manual

ST STM8S
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RM0016 Inter-integrated circuit (I
2
C) interface
Doc ID 14587 Rev 8 293/449
21.7 I
2
C registers
21.7.1 Control register 1 (I2C_CR1)
Address offset: 0x00
Reset value: 0x00
76 5 43210
NOSTRETCH ENGC
Reserved
PE
rw rw rw
Bit 7 NOSTRETCH: Clock stretching disable (Slave mode)
This bit is used to disable clock stretching in slave mode when ADDR or BTF flag is set, until it is
reset by software.
0: Clock stretching enabled
1: Clock stretching disabled
Bit 6 ENGC: General call enable
0: General call disabled. Address 0x00 is NACKed.
1: General call enabled. Address 0x00 is ACKed.
Bits 5:1 Reserved
Bit 0 PE: Peripheral enable
0: Peripheral disable
1: Peripheral enable: the corresponding I/Os are selected as alternate functions.
Note: If this bit is reset while a communication is on going, the peripheral is disabled at the end of the
current communication, when back to IDLE state.
All bit resets due to PE=0 occur at the end of the communication.

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ST STM8S Specifications

General IconGeneral
BrandST
ModelSTM8S
CategoryMicrocontrollers
LanguageEnglish

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