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16-bit advanced control timer (TIM1) RM0016

200/449 Doc ID 14587 Rev 8

17.7.12 Capture/compare mode register 4 (TIM1_CCMR4)

Address offset: 0xB

Reset value: 0x00

Refer to the CCMR1 register description above.

Channel configured in output

Channel configured in input

76543210

OC4CE OC4M[2:0] OC4PE OC4FE CC4S[1:0]

rw rw rw rw rw rw rw rw

Bit 7 OC4CE: Output compare 4 clear enable

Bits 6:4 OC4M[2:0]: Output compare 4 mode

Bit 3 OC4PE: Output compare 4 preload enable

Bit 2 OC4FE: Output compare 4 fast enable

Bits 1:0 CC4S[1:0]: Capture/compare 4 selection

This bitfield defines the direction of the channel (input/output) and the used input.

00: CC4 channel is configured as output

01: CC4 channel is configured as input, IC4 is mapped on TI4FP4

10: CC4 channel is configured as input, IC4 is mapped on TI3FP4

11: Reserved

Note: CC4S bits are writable only when the channel is off (CC4E and CC4NE = 0 and updated in

TIM1_CCER2).

76543210

IC4F[3:0] IC4PSC[1:0] CC4S[1:0]

rw rw rw rw rw rw rw rw

Bits 7:4 IC4F: Input capture 4 filter

Bits 3:2 IC4PSC[1:0]: Input capture 4 prescaler

Bits 1:0 CC4S[1:0]: Capture/compare 4 selection

This bitfield defines the direction of the channel (input/output) and the used input.

00: CC4 channel is configured as output.

01: CC4 channel is configured as input, IC4 is mapped on TI4FP4.

10: CC4 channel is configured as input, IC4 is mapped on TI3FP4.

11: Reserved

Note: CC4S bits are writable only when the channel is off (CC4E and CC4NE = 0 and updated in

TIM1_CCER2).

ST STM8S Reference Manual

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