ST STM8S Reference Manual

16-bit advanced control timer (TIM1) RM0016
152/449 Doc ID 14587 Rev 8
17.4.4 External clock source mode 2
The counter can count at each rising or falling edge on the ETR. This mode is selected by
writing ECE = 1 in the TIM1_ETR register.
The Figure 47 gives an overview of the external trigger input block.
Figure 47. External trigger input block diagram
Procedure
Use the following procedure to configure the up-counter and, for example, to count once
every two rising edges on the ETR:
1. As no filter is needed in this example, write ETF[3:0] = 0000 in the TIM1_ETR register.
2. Set the prescaler by writing ETPS[1:0] = 01 in the TIM1_ETR register.
3. Select rising edge detection on the ETR pin by writing ETP = 0 in the TIM1_ETR
register.
4. Enable external clock mode 2 by writing ECE = 1 in the TIM1_ETR register.
5. Enable the counter by writing CEN = 1 in the TIM1_CR1 register.
The counter counts once every two ETR rising edges.
The delay between the rising edge on the ETR and the actual reset of the counter is due to
the resynchronization circuit on the external trigger signal (ETRP).
Figure 48. Control circuit in external clock mode 2
ETR
0
1
TIM1_ETR
ETP
divider
/1, /2, /4, /8
ETPS[1:0]
ETRP
filter
ETF[3:0]
down-counter
f
MASTER
TIM1_ETR
TIM1_ETR
ETR pin
f
MASTER
encoder
mode
external clock
mode 1
external clock
mode 2
internal clock
mode
ETRF
TRGI
TI1F
TI2F
or
or
or
(internal clock)
CK_PSC
TIM1_ETR
ECE
TIM1_SMCR
SMS[2:0]
COUNTER CLOCK = CK_CNT = CK_PSC
COUNTER REGISTER
35 3634
ETR
CNT_EN
f
MASTER
ETRP
ETRF

ST STM8S Specifications

General

Brand	ST
Model	STM8S
Category	Microcontrollers
Language	English