ST STM8S Reference Manual

16-bit advanced control timer (TIM1) RM0016
194/449 Doc ID 14587 Rev 8
17.7.8 Event generation register (TIM1_EGR)
Address offset: 0x07
Reset value: 0x00
76543210
BG TG COMG CC4G CC3G CC2G CC1G UG
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Bit 7 BG: Break generation
This bit is set by software to generate an event. It is automatically cleared by hardware.
0: No action
1: A break event is generated. The MOE bit is cleared and the BIF flag is set. An interrupt is
generated if enabled by the BIE bit.
Bit 6 TG: Trigger generation
This bit is set by software to generate an event. It is automatically cleared by hardware.
0: No action
1: The TIF flag is set in TIM1_SR1 register. An interrupt is generated if enabled by the TIE bit.
Bit 5 COMG: Capture/compare control update generation
This bit can be set by software and is automatically cleared by hardware.
0: No action
1: When the CCPC bit in the TIM1_CR2 register is set, it allows the CCiE, CCiNE CCiP, C C iNP, and
OCiM bits to be updated.
Note: This bit acts only on channels that have a complementary output.
Bit 4 CC4G: Capture/compare 4 generation
Refer to CC1G description.
Bit 3 CC3G: Capture/compare 3 generation
Refer to CC1G description.
Bit 2 CC2G: Capture/compare 2 generation
Refer to CC1G description.
Bit 1 CC1G: Capture/compare 1 generation.
This bit is set by software to generate an event. It is automatically cleared by hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If the CC1 channel is configured in output mode:
The CC1IF flag is set and the corresponding interrupt request is sent if enabled.
If the CC1 channel is configured in input mode:
The current value of the counter is captured in the TIM1_CCR1 register. The CC1IF flag is set, and
the corresponding interrupt request is sent if enabled. The CC1OF flag is set if the CC1IF flag is
already high.
Bit 0 UG: Update generation
This bit can be set by software and is automatically cleared by hardware.
0: No action
1: Re-initializes the counter and generates an update of the registers. Note that the prescaler
counter is also cleared. The counter is cleared if center-aligned mode is selected or if DIR = 0 (up-
counting). Otherwise, it takes the auto-reload value (TIM1_ARR) if DIR = 1 (down-counting).

ST STM8S Specifications

General

Brand	ST
Model	STM8S
Category	Microcontrollers
Language	English