RM0016 16-bit advanced control timer (TIM1)
Doc ID 14587 Rev 8 141/449
Read operations to the TIM1_PSCR registers access the preload registers, so no special
care needs to be taken to read them.
17.3.4 Up-counting mode
In up-counting mode, the counter counts from 0 to a user-defined compare value (content of
the TIM1_ARR register). It then restarts from 0 and generates a counter overflow event and
a UEV if the UDIS bit is 0 in the TIM1_CR1 register.
Figure 34 shows an example of this counting mode.
Figure 34. Counter in up-counting mode
An update event can also be generated by setting the UG bit in the TIM1_EGR register
(either by software or by using the trigger controller).
The UEV can be disabled by software by setting the UDIS bit in the TIM1_CR1 register. This
is to avoid updating the shadow registers while writing new values in the preload registers.
No UEV occurs until the UDIS bit has been written to 0. Note that the counter and the
prescaler restart counting from 0 but, the prescaler division factor does not change. In
addition, if the URS bit (update request selection) in the TIM1_CR1 register is set, setting
the UG bit generates an UEV without setting the UIF flag. Consequently, no interrupt
request is sent. This avoids generating both update and capture interrupts when clearing the
counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIM1_SR1 register) is set (depending on the URS bit):
● The auto-reload shadow register is updated with the preload value (TIM1_ARR).
● The buffer of the prescaler is reloaded with the preload value (content of the
TIM1_PSCR register).
Figure 35 and Figure 36 show two examples of the counter behavior for different clock
frequencies when TIM1_ARR = 0x36.
In Figure 35, the prescaler divider is set to 2, so the counter clock (CK_CNT) frequency is at
half the frequency of the prescaler clock source (CK_PSC). The auto-reload preload is
disabled (ARPE = 0). Consequently, the shadow register is immediately changed and
counter overflow occurs when upcounting reaches 0x36. This generates a UEV.
Counter
TIMx_ARR
OverflowOverflow Overflow
Overflow
0
Time
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