Analog/digital converter (ADC) RM0016
436/449 Doc ID 14587 Rev 8
24.11.17 ADC watchdog control register high (ADC_AWCRH)
Address offset: 0x2E
Reset value: 0x00
Note: This register is not available for ADC2.
24.11.18 ADC watchdog control register low (ADC_AWCRL)
Address offset: 0x2F
Reset value: 0x00
Note: This register is not available for ADC2.
76543210
Reserved
AWEN[9:8]
rw rw
Bits 7:2 Reserved, must be kept cleared.
Bits 1:0 AWEN[9:8] Analog watchdog enable bits 9:8
These bits are set and cleared by software.
In buffered continuous mode (DBUF=1, CONT=1) and in scan mode (SCAN=1)
the AWENx bits enable the analog watchdog function for each of the 10 data
buffer registers.
0: Analog watchdog disabled in data buffer register x.
1: Analog watchdog enabled in data buffer register x.
76543210
AWEN[7:0]
rw rw rw rw rw rw rw rw
Bits 7:0 AWEN[7:0] Analog watchdog enable bits 7:0
These bits are set and cleared by software.
In buffered continuous mode (DBUF=1, CONT=1) and in scan mode (SCAN=1)
the AWENx bits enable the analog watchdog function for each of the 10 data
buffer registers.
0: Analog watchdog disabled in data buffer register x.
1: Analog watchdog enabled in data buffer register x.
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