ST STM8S

16-bit general purpose timers (TIM2, TIM3, TIM5) RM0016
226/449 Doc ID 14587 Rev 8
18.6.4 Interrupt enable register (TIMx_IER)
Address offset: 0x01 or 0x03 (TIM2), 0x01 (TIM3), 0x03 (TIM5); for TIM2 address see
Section
Reset value: 0x00
76543210
Reserved
TIE
Reserved
CC3IE CC2IE CC1IE UIE
rw rw rw rw rw
Bits 7 Reserved
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Note: In TIM2/TIM3 this bit is reserved.
Bits 5:4 Reserved, must be kept cleared
Bit 3 CC3IE: Capture/compare 3 interrupt enable
0: CC3 interrupt disabled
1: CC3 interrupt enabled
Bit 2 CC2IE: Capture/compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled