Interrupt controller (ITC) RM0016
58/449 Doc ID 14587 Rev 8
6 Interrupt controller (ITC)
6.1 ITC introduction
● Management of hardware interrupts
– External interrupt capability on most I/O pins with dedicated interrupt vector and
edge sensitivity setting per port
– Peripheral interrupt capability
● Management of software interrupt (TRAP)
● Nested or concurrent interrupt management with flexible interrupt priority and level
management:
– Up to 4 software programmable nesting levels
– Up to 32 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
– 1 non-maskable top level hardware interrupt (TLI)
This interrupt management is based on:
● Bit I1 and I0 of the CPU Condition Code register (CCR)
● Software priority registers (ITC_SPRx)
● Reset vector address 0x00 8000 at the beginning of program memory. In devices with
boot ROM, the reset initialization routine is programmed in ROM by
STMicroelectronics.
● Fixed interrupt vector addresses located at the high addresses of the memory map
(0x00 8004 to 0x00 807C) sorted by hardware priority order.
6.2 Interrupt masking and processing flow
The interrupt masking is managed by bits I1 and I0 of the CCR register and by the
ITC_SPRx registers which set the software priority level of each interrupt vector (see
Table 8 ). The processing flow is shown in Figure 13.
When an interrupt request has to be serviced:
1. Normal processing is suspended at the end of the current instruction execution.
2. The PC, X,Y, A and CCR registers are saved onto the stack.
3. Bits I1 and I0 of CCR register are set according to the values in the ITC_SPRx registers
corresponding to the serviced interrupt vector.
4. The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched .
The interrupt service routine should end with the IRET instruction which causes the content
of the saved registers to be recovered from the stack. As a consequence of the IRET
instruction, bits I1 and I0 are restored from the stack and the program execution resumes.
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