ST STM8S Reference Manual

RM0016 Interrupt controller (ITC)
Doc ID 14587 Rev 8 69/449
6.9.3 External interrupt control register 1 (EXTI_CR1)
Address offset: 0x00
Reset value: 0x00
76543210
PDIS[1:0] PCIS[1:0] PBIS[1:0] PAIS[1:0]
rw rw rw rw
Bits 7:6 PDIS[1:0]: Port D external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3).
They define the sensitivity of Port D external interrupts.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge
Bits 5:4 PCIS[1:0]: Port C external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3).
They define the sensitivity of Port C external interrupts.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge
Bits 3:2 PBIS[1:0]: Port B external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3).
They define the sensitivity of Port B external interrupts.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge
Bits 1:0 PAIS[1:0]: Port A external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3).
They define the sensitivity of Port A external interrupts.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge

ST STM8S Specifications

General

Brand	ST
Model	STM8S
Category	Microcontrollers
Language	English