RM0016 16-bit advanced control timer (TIM1)
Doc ID 14587 Rev 8 147/449
17.3.7 Repetition down-counter
Section 17.3: TIM1 time base unit describes how the UEV is generated with respect to
counter overflows/underflows. It is generated only when the repetition down-counter
reaches zero. This can be useful while generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIM1_ARR auto-reload register, TIM1_PSCR prescaler register, and TIM1_CCRx
capture/compare registers in compare mode) every ‘n’ counter overflow or underflow, where
N is the value in the TIM1_RCR repetition counter register.
The repetition down-counter is decremented:
● At each counter overflow in up-counting mode
● At each counter underflow in down-counting mode
● At each counter overflow and at each counter underflow in center-aligned mode.
Although this limits the maximum number of repetitions to 128 PWM cycles, it makes it
possible to update the duty cycle twice per PWM period. When refreshing compare
registers only once per PWM period in center-aligned mode, maximum resolution is
2 x t
CK_PSC
due to the symmetry of the pattern.
The repetition down-counter is an auto-reload type, the repetition rate of which is maintained
as defined by the TIM1_RCR register value (refer to Figure 42). When the UEV is generated
by software (by setting the UG bit in the TIM1_EGR register) or by hardware (through the
clock/trigger controller), it occurs immediately irrespective of the value of the repetition
down-counter. The repetition down-counter is reloaded with the content of the TIM1_RCR
register.
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