Clock control (CLK) RM0016
98/449 Doc ID 14587 Rev 8
9.9.11 HSI clock calibration trimming register (CLK_HSITRIMR)
Address offset: 0x0C
Reset value: 0x00
76543210
Reserved
HSITRIM[3:0]
rw rw rw rw
Bits 7:4 Reserved, must be kept cleared.
Bits 3:0 HSITRIM[3:0] HSI trimming value
These bits are written by software to fine tune the HSI calibration.
Note: In high density STM8S and STM8A devices, only bits 2:0 are available.
In other devices, bits 3:0 are available to achieve a better HSI resolution. Compatibility with bits
2:0 can be selected through options bytes (refer to datasheet).
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