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RM0016 16-bit advanced control timer (TIM1)

Doc ID 14587 Rev 8 193/449

17.7.7 Status register 2 (TIM1_SR2)

Address offset: 0x06

Reset value: 0x00

Bit 0 UIF: Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update has occurred

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow or underflow if UDIS = 0 in the TIM1_CR1 register

– When CNT is re-initialized by software using the UG bit in TIM1_EGR register, if URS = 0

and UDIS = 0 in the TIM1_CR1 register.

– When CNT is re-initialized by a trigger event (refer to the TIM1_SMCR register description),

if URS = 0 and UDIS = 0 in the TIM1_CR1 register.

76543210

Reserved

CC4OF CC3OF CC2OF CC1OF

Reserved

rc_w0 rc_w0 rc_w0 rc_w0

Bits 7:5 Reserved, must be kept cleared

Bit 4 CC4OF: Capture/compare 4 overcapture flag

Refer to CC1OF description

Bit 3 CC3OF: Capture/compare 3 overcapture flag

Refer to CC1OF description

Bit 2 CC2OF: Capture/compare 2 overcapture flag

Refer to CC1OF description

Bit 1 CC1OF: Capture/compare 1 overcapture flag

This flag is set by hardware only when the corresponding channel is configured in input capture

mode. It is cleared by software by writing it to 0.

0: No overcapture has been detected

1: The counter value has been captured in TIM1_CCR1 register while CC1IF flag was already set

Bit 0 Reserved, must be kept cleared.

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