ST STM8S Reference Manual

Analog/digital converter (ADC) RM0016
428/449 Doc ID 14587 Rev 8
24.11.4 ADC configuration register 1 (ADC_CR1)
Address offset: 0x21
Reset value: 0x00
76543210
Reserved
SPSEL[2:0]
Reserved
CONT ADON
rw rw rw rw rw
Bit 7 Reserved, always read as 0.
Bits 6:4 SPSEL[2:0]: Prescaler selection
These control bits are written by software to select the prescaler division factor.
000: f
ADC
= f
MASTER
/2
001: f
ADC
= f
MASTER
/3
010: f
ADC
= f
MASTER
/4
011: f
ADC
= f
MASTER
/6
100: f
ADC
= f
MASTER
/8
101: f
ADC
= f
MASTER
/10
110: f
ADC
= f
MASTER
/12
111: f
ADC
= f
MASTER
/18
See Section 24.5.2 on page 414.
Note: It is recommended to change the SPSEL bits when ADC is in power down.
This is because internally there can be a glitch in the clock during this
change. Otherwise the user is required to ignore the 1st converted result if
the change is done when ADC is not in power down.
Bits 3:2 Reserved, always read as 0.
Bit 1 CONT: Continuous conversion
This bit is set and cleared by software. If set, conversion takes place
continuously till this bit is reset by software.
0: Single conversion mode
1: Continuous conversion mode
Bit 0 ADON: A/D Converter on/off
This bit is set and reset by software. This bit must be written to wake up the
ADC from power down mode and to trigger the start of conversion. If this bit
holds a value of 0 and a 1 is written to it then it wakes the ADC from power
down mode. Conversion starts when this bit holds a value of 1 and a 1 is written
to it. As soon as the ADC is powered on, the output stage of the selected
channel is disabled.
0: Disable ADC conversion/calibration and go to power down mode.
1: Enable ADC and to start conversion
Note: If any other bit in this register apart from ADON is changed at the same
time, then conversion is not triggered. This is to prevent triggering an
erroneous conversion.

ST STM8S Specifications

General

Brand	ST
Model	STM8S
Category	Microcontrollers
Language	English