Inter-integrated circuit (I
2
C) interface RM0016
286/449 Doc ID 14587 Rev 8
Master receiver
Following the address transmission and after clearing ADDR, the I
2
C interface enters
Master Receiver mode. In this mode the interface receives bytes from the SDA line into the
DR register via the internal shift register. After each byte the interface generates in
sequence:
● An acknowledge pulse if the ACK bit is set
● The RXNE bit is set and an interrupt is generated if the ITEVTEN and ITBUFEN bits
are set ().
If the RXNE bit is set and the data in the DR register was not read before the end of the next
data reception, the BTF bit is set by hardware and the interface waits for the BTF bit to be
cleared by reading I2C_SR1 and then I2C_DR, stretching SCL low.
Closing the communication
Method 1: This method is for the case when the I2C is used with interrupts that have the
highest priority in the application.
The master sends a NACK for the last byte received from the slave. After receiving this
NACK, the slave releases the control of the SCL and SDA lines. Then the master can send
a Stop/Re-Start condition.
● In order to generate the non-acknowledge pulse after the last received data byte, the
ACK bit must be cleared just after reading the second last data byte (after second last
RXNE event).
● In order to generate the Stop/Re-Start condition, software must set the STOP/ START
bit just after reading the second last data byte (after the second last RXNE event).
● In case a single byte is to be received, the Acknowledge deactivation and the STOP
condition generation are made just after EV6 (in EV6-1 just after ADDR is cleared).
After the Stop condition generation, the interface goes automatically back to slave mode
(MSL bit cleared).
Method 1: This method is for the case when the I2C is used with interrupts that have the
highest priority in the application.
Figure 105. Method 1: transfer sequence diagram for master receiver
1. Legend:
S= Start, S
r
= Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge,
EVx= Event (with interrupt if ITEVTEN=1)
EV5: SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: ADDR=1, cleared by reading SR1 register followed by reading SR3. In 10-bit master receiver mode, this sequence
should be followed by writing CR2 with START = 1.
7-bit Master Receiver
10-bit Master Receiver
S Address A Data1 A Data2 A
(1)
1. In case of a single byte to be received, it is a NACK
.....
DataN NA P
EV5 EV6 EV6_1 EV7 EV7 EV7_1 EV7
S Header A Address A
EV5 EV9 EV6
S
r
Header A Data1 A
.....
DataN NA P
EV5 EV6 EV6_1 EV7 EV7_1 EV7
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