ST STM8S Reference Manual

Revision history RM0016
440/449 Doc ID 14587 Rev 8
15-Jan-2009 4
Removed memory and register map (information transferred to
datasheets)
Register absolute addresses replaced by offsets. (refer now to
register map in datasheet for the base addresses).
Added Note related to TLI interrupt in Section 6.2.1 on page 60.
Added TLI in Section 6.5: Concurrent and nested interrupt
management.
Updated Flash program density to 32 - 128 Kbytes for high density
STM8S devices in Section 4: Flash program memory and data
EEPROM.
Updated size of STM8S option byte area in Section 4.4: Memory
organization and Figure 6, Figure 7, and Figure 8.
Updated maximum value of UBC in Figure 11.Added information on
DATA area programming on devices with and without RWW
capability in Section 4.6.2: Byte programming and Section 4.6.4:
Block programming.
Added HVOFF in: Fast block programming, : Fast block
programming, and Section 4.8.8: Flash status register
(FLASH_IAPSR). Updated bitfield access types in Section 4.8.8:
Flash status register (FLASH_IAPSR) on page 55.
Table 6: Memory access versus programming method: removed NMI
and TRAP vectors, modified access for option bytes in ICP/SWIM
mode/ROP enabled, and UBC ROP disabled.
Updated Table 28: Watchdog timeout period (LSI clock frequency =
128 kHz) on page 123
Updated Table 29: Approximate timeout duration on page 128
Table 30: Window watchdog timing diagram on page 129
Updated Note 8 on page 300
10-Aug-2009 5
Added note to Section 4.4: Memory organization.
Added Section 4.4.2: Memory access/ wait state configuration.
Updated maximum value of UCB[7:0] in Figure 2: Page 255 is
reserved for data EEPROM.
Added note 1 below Figure 10. Added note 1 and updated note 3
below Figure 11.
Check in PUL/DUL bits made mandatory in Section 4.5.2: Memory
access security system (MASS).
Added details in Section 4.6: Memory programming on word
programming in main program and DATA.
Updated Section 4.8.8: Flash status register (FLASH_IAPSR) on
page 55.
Added note to Section 9.1.2: HSI.
Updated Tabl e 17 (UART peripheral clock gating bit description
moved to datasheet).
Updated Table 20: Low power mode management on page 102
Updated management of hardware interrupts in Section 6.1: ITC
introduction.
Removed interrupt vector table (moved to datasheet)
Table 78. Document revision history (continued)
Date Revision Changes

ST STM8S Specifications

General

Brand	ST
Model	STM8S
Category	Microcontrollers
Language	English