ST STM8S Reference Manual

RM0016 Revision history
Doc ID 14587 Rev 8 441/449
10-Aug-2009
5
cont’d
Changed note in Section 6.9.2: Software priority register x
(ITC_SPRx) on page 68.
Updated AWU Section 12.3.2: Time base selection.
Removed description of timer input XOR feature (TI1S bit in
Section 17 and Section 18.
Updated trigger selection for and ETR description for TIM5 in
Section 18.
Updated MMS bits in Control register 2 (TIM5_CR2) and Control
register 2 (TIM6_CR2).
Updated TG bit of Event generation register (TIMx_EGR).
Added note on TIM2 and TIM4 register offsets inSection on page
239 and Section 19.6.10 on page 251
Section 21.4.3, Acknowledge failure (AF): Added “repeated start” to
master condition.
Modified Section 21.7.3: Frequency register (I2C_FREQR) on
page 296.
Added 6th step to UART Character transmission. Updated
UARTSingle byte communication.
Added Figure 115: TC/TXE behavior when transmitting.
Updated TC bit description in Section 22.7.1: Status register
(UART_SR).
Added Start bit detection and Section 22.3.5: Clock deviation
tolerance of the UART receiver in Section 22.3.3: Receiver.
Added a caution to Section 23.11.15: Mailbox registers.
Updated description of TGT in CAN mailbox data length control
register (CAN_MDLCR).
Changed alignment of threshold registers and added note for data
buffer base address in Section 24.11: ADC registers.
08-Dec-2009 6
Peripheral clock gating register 2 (CLK_PCKENR2): Replaced
address offset.
Table 20: Low power mode management: Updated peripheral
information for Active halt (--), Active halt with MVR auto power off (--
-), and Halt (----).
Repetition counter register (TIM1_RCR): Replaced the reset value.
Interrupt enable register (TIMx_IER): Corrected name of bit 3
(CC3IE) in register table.
Status register 1 (TIMx_SR1): Added description of bit 3 (CC3IF) to
register description table.
Figure 93: Data clock timing diagram: Removed “from master” and
“from slave” beneath MISO and MOSI respectively.
Section 20.3.5: Data transmission and reception procedures: timing
diagrams revised and description of receive-only mode expanded.
Added Section 20.3.8: Disabling the SPI
Master mode fault (MODF): SPE and MSTR bits can be returned to
their original state only after a MODF bit clearing sequence.
SPI interrupt control register (SPI_ICR): Removed notes relating to
the TXIE and RXIE bits.
Table 78. Document revision history (continued)
Date Revision Changes

ST STM8S Specifications

General

Brand	ST
Model	STM8S
Category	Microcontrollers
Language	English