ST STM8S Reference Manual

8-bit basic timer (TIM4, TIM6) RM0016
248/449 Doc ID 14587 Rev 8
19.6.5 Status register 1 (TIMx_SR)
Address offset: 0x02 or 0x04 (TIM4), 0x04 (TIM6); for TIM4 address see Section 19.6.10
Reset value: 0x00
19.6.6 Event generation register (TIMx_EGR)
Address offset: 0x03 or 0x05 (TIM4), 0x05 (TIM6); for TIM4 address see Section 19.6.10
Reset value: 0x00
76543210
Reserved
TIF
Reserved
UIF
rc_w0 rc_w0
Bit 7 Reserved, must be kept cleared
Bit 6 TIF: Trigger interrupt flag.
This flag is set by hardware on a trigger event (the active edge is detected on the TRGI signal,
both edges are detected if gated mode is selected). It is cleared by software.
0: No trigger event has occurred
1: Trigger interrupt pending.
Note: In TIM4 this bit is reserved.
Bits 5:1 Reserved, must be kept cleared
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update has occurred
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow if UDIS = 0 in the TIM4_CR1 register
– When CNT is re-initialized by software using the UG bit in the TIM4_EGR register, if URS = 0
and UDIS = 0 in the TIM4_CR1 register.
76543210
Reserved
TG
Reserved
UG
w w
Bit 7 Reserved, must be kept cleared
Bit 6 TG: Trigger generation
This bit is set by software to generate an event. It is automatically cleared by hardware.
0: No action
1: The TIF flag is set in TIM6_SR register. An interrupt is generated if enabled by the TIE bit
Note: In TIM4 this bit is reserved.
Bits 5:1 Reserved, must be kept cleared
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initializes the counter and generates an update of the registers. Note that the prescaler
counter is also cleared.

ST STM8S Specifications

General

Brand	ST
Model	STM8S
Category	Microcontrollers
Language	English