ST STM8S - Capture;Compare Register 4 High (TIM1_CCR4 H); Capture;Compare Register 4 Low (TIM1_CCR4 L)

16-bit advanced control timer (TIM1) RM0016
210/449 Doc ID 14587 Rev 8
17.7.28 Capture/compare register 4 high (TIM1_CCR4H)
Address offset: 0x1B
Reset value: 0x00
17.7.29 Capture/compare register 4 low (TIM1_CCR4L)
Address offset: 0x1C
Reset value: 0x00
76543210
CCR4[15:8]
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Bits 7:0 CCR4[15:8]: Capture/compare value (MSB)
If the CC4 channel is configured as output (CC4S bits in TIM1_CCMR4 register):
The value of CCR4 is loaded permanently into the actual capture/compare 4 register if the preload
feature is not enabled (OC4PE bit in TIM1_CCMR4). Otherwise, the preload value is copied in the
active capture/compare 4 register when a UEV occurs.The active capture/compare register contains
the value which is compared to the counter register, TIM1_CNT, and signalled on the OC4 output.
If the CC4 channel is configured as input (CC4S bits in TIM1_CCMR4 register):
The value of CCR4 is the counter value transferred by the last input capture 4 event (IC4).
76543210
CCR4[7:0]
rw rw rw rw rw rw rw rw
Bits 7:0 CCR4[7:0]: Capture/compare value (LSB)