Analog/digital converter (ADC) RM0016
426/449 Doc ID 14587 Rev 8
24.11.2 ADC data buffer register x low (ADC_DBxRL) (x=or 0..7 or 0..9)
Address offset: 0x01 + 2 * channel number
Reset value: 0x00
Note: Data buffer registers are not available for ADC2. The data buffer size and base address are
device dependent and are specified in the corresponding datasheet. Note that the data
buffer registers and the other ADC registers have different base addresses.
76543210
DBL[7:0]
rrrrrrrr
Bits 7:0 DBL[7:0] Data bits low
These bits are set/reset by hardware and are read only. When the ADC is in
buffered continuous or scan mode, they contain the low part of the A/D
conversion result, in right-aligned or left-aligned format depending on the
ALIGN bit.
Left Data Alignment
These bits contain the (eight ADC data width) LSB bits of the converted data.
Remaining bits of the register are tied to zero.
See Figure 164.
Right Data Alignment
These bits contain the eight LSB bits of the converted data.
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