RM0016 Revision history
Doc ID 14587 Rev 8 439/449
25 Revision history
Table 78. Document revision history
Date Revision Changes
27-May-2008 1 Initial release.
13-Aug-2008 2
Updated Section 2: Memory and register map on page 27:
introduced high, medium and low density categories; modified end
address for option bytes; updated RAM, data EEPROM and Flash
program memory densities.
Updated Figure 18: Reset circuit on page 73
Update min reset pulse from 300 to 500 ns in Section 8.2: Reset
circuit description on page 73
Updated Table 6: Memory access versus programming method on
page 50.
Reorganized Section 16 on page 132 to Section 19 on page 243
Renamed USART and LINUART to UART1, UART2 and UART3
combined in new Section 22 on page 307.
Updated CAN filter and external clock description in Section 23 on
page 362.
Renamed ADC to ADC1 and ADC2 in Section 24 on page 411
Updated Continuous scan mode on page 416
Updated Conversion on external trigger on page 418
22-Sep-2008 3
Updated Section 4: Flash program memory and data EEPROM.
Changed name of SWUAH bit to REGAH in Section 9.9.1: Internal
clock register (CLK_ICKR) on page 89.
Modified LSI frequency measurement in Section 11.1 on page 105
Modified Peripheral clock gating register 1 (CLK_PCKENR1) on
page 94
Modified Section 11.8.2: Slope control on page 110.
Added description of TIM5, TIM6 in Section 16: Timer overview,
Section 18: 16-bit general purpose timers (TIM2, TIM3, TIM5) and
Section 19: 8-bit basic timer (TIM4, TIM6).
Updated Section 24.5.6: Analog watchdog.
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