ST STM8S

Clock control (CLK) RM0016
94/449 Doc ID 14587 Rev 8
9.9.7 Peripheral clock gating register 1 (CLK_PCKENR1)
Address offset: 0x07
Reset value: 0xFF
76543210
PCKEN1[7:0]
rw rw rw rw rw rw rw rw
Bits 7:0 PCKEN1[7:0]: Peripheral clock enable
These bits are written by software to enable or disable the f
MASTER
clock to the corresponding
peripheral (see Ta bl e 1 7).
0: f
MASTER
to peripheral disabled
1: f
MASTER
to peripheral enabled
Table 17. Peripheral clock gating bits
Control bit Peripheral
PCKEN17 TIM1
PCKEN16 TIM3
PCKEN15 TIM2/TIM5 (product dependent)
PCKEN14 TIM4/ TIM6 (product dependent)
PCKEN13
UART1/2/3 (product dependent, see datasheet
for bit assignment table)
PCKEN12
PCKEN11 SPI
PCKEN10 I
2
C