ST STM8S Reference Manual

Reset (RST) RM0016
76/449 Doc ID 14587 Rev 8
8.4 RST register description
8.4.1 Reset status register (RST_SR)
Address offset: 0x00
Reset value: 0xXX
8.5 RST register map
Refer to the corresponding datasheet for the base address.
76543210
Reserved
EMCF SWIMF ILLOPF IWDGF WWDGF
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 7:5 Reserved.
Bit 4 EMCF: EMC reset flag
This bit is set by hardware and cleared by software writing “1”.
0: No EMC reset occurred
1: An EMC reset occurred (possible cause: complementary register or option byte mismatch).
Bit 3 SWIMF: SWIM reset flag
This bit is set by hardware and cleared by software writing “1”.
0: No SWIM reset occurred
1: A SWIM reset occurred
Bit 2 ILLOPF: Illegal opcode reset flag
This bit is set by hardware and cleared by software writing “1”.
0: No ILLOP reset occurred
1: An ILLOP reset occurred
Bit 1 IWDGF: Independent Watchdog reset flag
This bit is set by hardware and cleared by software writing “1”.
0: No IWDG reset occurred
1: An IWDG reset occurred
Bit 0 WWDGF: Window Watchdog reset flag
This bit is set by hardware and cleared by software writing “1”.
0: No WWDG reset occurred
1: An WWDG reset occurred
Table 13. RST register map
Address
offset
Register Name765432 1 0
0x00
RST_SR
Reset value
-
x
-
x
-
x
EMCF
x
SWIMF
x
ILLOPF
x
IWDGF
x
WWDGF
x

ST STM8S Specifications

General

Brand	ST
Model	STM8S
Category	Microcontrollers
Language	English