16-bit advanced control timer (TIM1) RM0016
140/449 Doc ID 14587 Rev 8
17.3.1 Reading and writing to the 16-bit counter
There is no buffering when writing to the counter. Both TIM1_CNTRH and TIM1_CNTRL
can be written at any time, so it is suggested not to write a new value into the counter while
it is running to avoid loading an incorrect intermediate content.
An 8-bit buffer is implemented for the read. Software must read the MS byte first, after which
the LS byte value is buffered automatically (see Figure 33). This buffered value remains
unchanged until the 16-bit read sequence is completed.
Note: Do not use the LDW instruction to read the 16-bit counter. It reads the LS byte first and
returns an incorrect result.
Figure 33. 16-bit read sequence for the counter (TIM1_CNTR)
17.3.2 Write sequence for 16-bit TIM1_ARR register
16-bit values are loaded in the TIM1_ARR register through preload registers. This must be
performed by two write instructions, one for each byte. The MS byte must be written first.
The shadow register update is blocked as soon as the MS byte has been written, and stays
blocked until the LS byte has been written. Do not use the LDW instruction as this writes the
LS byte first which produces incorrect results.
17.3.3 Prescaler
The prescaler implementation is as follows:
The TIM1 prescaler is based on a 16-bit counter controlled through a 16-bit register (in
TIM1_PSCR register). It can be changed on the fly as this control register is buffered. It can
divide the counter clock frequency by any factor between 1 and 65536.
The counter clock frequency is calculated as follows:
f
CK_CNT
= f
CK_PSC
/(PSCR[15:0]+1)
The prescaler value is loaded through a preload register. The shadow register, which
contains the current value to be used, is loaded as soon as the LS byte has been written.
To update the 16-bit prescaler, load two bytes in separate write operations starting with the
MSB. Do not use the LDW instruction for this purpose as it writes the LSB first.
The new prescaler value is taken into account in the following period (after the next counter
update event).
is buffered
Read
At t0
Read
Returns the buffered
LS byte value at t0
At t0 +Dt
Other
instructions
Beginning of the sequence
Sequence completed
LS byte
LS byte
MS byte