Interrupt controller (ITC) RM0016
64/449 Doc ID 14587 Rev 8
6.5.2 Nested interrupt management mode
In this mode, interrupts are allowed during interrupt routines. This mode is activated as soon
as an interrupt priority level lower than level 3 is set.
The hardware priority is given in the following order from the lowest to the highest priority,
that is: MAIN, IT4, IT3, IT2, IT1, IT0, and TRAP.
The software priority is configured for each interrupt vector by setting the corresponding
I1_x and I0_x bits of the ITC_SPRx register. I1_x and I0_x bits have the same meaning as
I1 and I0 bits of the CCR register (see Ta bl e 10 ).
Level 0 can not be programmed (I1_x=1, I0_x=0). In this case, the previously stored value is
kept. For example: if previous value is 0xCF, and programmed value equals 64h, the result is
44h.
The RESET and TRAP vectors have no software priorities. When one is serviced, bits I1
and I0 of the CCR register are both set.
Caution: If bits I1_x and I0_x are modified while the interrupt x is executed, the device operates as
follows: if the interrupt x is still pending (new interrupt or flag not cleared) and the new
software priority is higher than the previous one, then the interrupt x is re-entered.
Otherwise, the software priority remains unchanged till the next interrupt request (after the
IRET of the interrupt x).
During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI
instructions change the current software priority till the next IRET instruction or one of the
previously mentioned instructions is issued. See Section 6.7 for the list of dedicated
interrupt instructions.
Figure 16 shows an example of nested interrupt management mode.
Warning: A stack overflow may occur without notifying the software of
the failure.
Table 10. Vector address map versus software priority bits
Vector address ITC_SPRx bits
0x00 8008h I1_0 and I0_0 bits
(1)
1. ITC_SPRx register bits corresponding to the TLI can be read and written. However they are not significant
in the interrupt process management.
0x00 800Ch I1_1 and I0_1 bits
... ...
0x00 807Ch I1_29 and I0_29 bits
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