ST STM8S Reference Manual

Inter-integrated circuit (I
2
C) interface RM0016
304/449 Doc ID 14587 Rev 8
21.7.12 Clock control register high (I2C_CCRH)
Address offset: 0x0C
Reset value: 0x00
Note: The CCR registers must be configured only when the I²C is disabled (PE=0).
f
MASTER
= multiple of 10 MHz is required to generate Fast clock at 400 kHz.
f
MASTER
≥ 1 MHz is required to generate Standard clock at 100 kHz.
76543210
F/S DUTY
Reserved
CCR[11:8]
rw rw rw
Bit 7 F/S: I2C master mode selection
0: Standard mode I2C
1: Fast mode I2C
Bit 6 DUTY: Fast mode duty cycle
0: Fast mode t
low
/t
high
= 2
1: Fast mode t
low
/t
high
= 16/9 (see CCR)
Bits 5:4 Reserved
Bits 3:0 CCR[11:8]: Clock control register in Fast/Standard mode (Master mode)
Controls the SCLH clock in master mode.
– Standard mode:
Period(I2C) = 2 * CCR * t
MASTER
t
high
= CCR * t
MASTER
t
low
= CCR * t
MASTER
– Fast mode:
If DUTY = 0:
Period(I2C) = 3 * CCR * t
MASTER
t
high
= CCR * t
MASTER
t
low
= 2 * CCR * t
MASTER
If DUTY = 1: (to reach 400 kHz)
Period(I2C) = 25 * CCR * t
MASTER
t
high
= 9 * CCR * t
MASTER
t
low
= 16 * CCR * t
MASTER
For instance: in standard mode, to generate a 100 kHz SCL frequency:
If FREQR = 08, t
MASTER
= 125 ns so CCR must be programmed with 0x28
(0x28 <=> 40 x 125 ns = 5000 ns.)
Note: t
high
= t
r(SCL)
+ t
w(SCLH)
. See device datasheet for the definitions of parameters
t
low
= t
f(SCL)
+ t
w(SCLL)
. See device datasheet for the definitions of parameters
These timings are without filters.

ST STM8S Specifications

General

Brand	ST
Model	STM8S
Category	Microcontrollers
Language	English