ST STM8S Reference Manual

Universal asynchronous receiver transmitter (UART) RM0016
340/449 Doc ID 14587 Rev 8
When checking this time-out, the slave node is desynchronized for the reception of the LIN
Break and Synch fields. Consequently, a margin must be allowed, taking into account the
worst case: This occurs when the LIN identifier lasts exactly 10 TBIT_MASTER periods. In
this case, the LIN Break and Synch fields last 49 - 10 = 39 TBIT_MASTER periods.
Assuming the slave measures these first 39 bits with a desynchronized clock of 15.5%. This
leads to a maximum allowed Header Length of:
39 x (1/0.845) TBIT_MASTER + 10 TBIT_MASTER
= 56.15 TBIT_SLAVE
A margin is provided so that the time-out occurs when the header length is greater than 57
TBIT_SLAVE periods. If it is less than or equal to 57 TBIT_SLAVE periods, then no time-out
occurs.
Mute mode and errors
In mute mode, if an LHE error occurs during the analysis of the LIN Synch Field or if a LIN
Header Time-out occurs then the LHE bit is set but it does not wake up from mute mode. In
this case, the current header analysis is discarded. If needed, the software has to reset the
LSF bit. Then the UART searches for a new LIN header.
In mute mode, if a framing error occurs on a data (which is not a break), it is discarded and
the FE bit is not set.
Any LIN header which respects the following conditions causes a wake-up from mute mode:
● A valid LIN Break and Delimiter
● A valid LIN Synch Field (without deviation error)
● A LIN Identifier Field without framing error. Note that a LIN parity error on the LIN
Identifier Field does not prevent wake-up from mute mode.
● No LIN Header Time-out should occur during Header reception.
22.4.3 Slave mode with automatic resynchronization enabled
This mode is similar to slave mode as described in Section 22.4.2: Slave mode with
automatic resynchronization disabled, with the addition of automatic resynchronization
enabled by the LASE bit. In this mode UART adjusts the baudrate generator after each
Synch Field reception.
Note: This feature is only available in UART2 and UART3.
Automatic resynchronization
When automatic resynchronization is enabled, after each LIN Break, the time duration
between 5 falling edges on RDI is sampled on f
MASTER
and the result of this measurement
is stored in an internal 19-bit register called SM (not user accessible) (See Figure 134).
Then the UARTDIV value (and its associated BRR1 and BRR2 registers) are automatically
updated at the end of the fifth falling edge. During LIN Synch field measurement, the UART
state machine is stopped and no data is transferred to the data register.

ST STM8S Specifications

General

Brand	ST
Model	STM8S
Category	Microcontrollers
Language	English