RM0016 16-bit general purpose timers (TIM2, TIM3, TIM5)
Doc ID 14587 Rev 8 235/449
18.6.12 Capture/compare enable register 2 (TIMx_CCER2)
Address offset: 0x09 or 0x0B (TIM2), 0x0B (TIM5); for TIM2 address see Section
Reset value: 0x00
Note: This register is not available in TIM3.
18.6.13 Counter high (TIMx_CNTRH)
Address offset: 0x0A or 0x0C (TIM2), 0x08 (TIM3), 0x0C (TIM5); for TIM2 address see
Section
Reset value: 0x00
Bit 0 CC1E: Capture/Compare 1 output Enable.
CC1 channel configured as output:
0: Off - OC1 is not active.
1: On - OC1 signal is output on the corresponding output pin.
CC1 channel configured as input:
In this case, this bit determines if a capture of the counter value can be made in the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled
76543210
Reserved
CC3P CC3E
rw rw
Bits 7:2 Reserved
Bit 1 CC3P: Capture/compare 3 output polarity
Refer to CC1P description.
Bit 0 CC3E: Capture/compare 3 output enable
Refer to CC1E description.
76543210
CNT[15:8]
rw rw rw rw rw rw rw rw
Bits 7:0 CNT[15:8]: Counter value (MSB)
To Next Page
Loading...
Need help?
General
