RM0016 16-bit general purpose timers (TIM2, TIM3, TIM5)
Doc ID 14587 Rev 8 237/449
18.6.17 Auto-reload register low (TIMx_ARRL)
Address offset: 00x0E or 0x10 (TIM2), 0x0C (TIM3), 0x10 (TIM5); for TIM2 address see
Section
Reset value: 0xFF
18.6.18 Capture/compare register 1 high (TIMx_CCR1H)
Address offset: 00x0F or 0x11 (TIM2), 0x0D (TIM3), 0x11 (TIM5); for TIM2 address see
Section
Reset value: 0x00
76543210
ARR[7:0]
rw rw rw rw rw rw rw rw
Bits 7:0 ARR[7:0]: Auto-reload value (LSB)
76543210
CCR1[15:8]
rw rw rw rw rw rw rw rw
Bits 7:0 CCR1[15:8]: Capture/compare 1 value (MSB)
If the CC1 channel is configured as output (CC1S bits in TIMx_CCMR1 register):
The value of CCR1 is loaded permanently into the actual capture/compare 1 register if the preload
feature is not enabled (OC1PE bit in TIMx_CCMR1). Otherwise, the preload value is copied in the
active capture/compare 1 register when a UEV occurs. The active capture/compare register
contains the value which is compared to the counter register, TIMx_CNT, and signalled on the OC1
output.
If the CC1 channel is configured as input (CC1S bits in TIMx_CCMR1 register):
The value of CCR1 is the counter value transferred by the last input capture 1 event (IC1). In this
case, these bits are read only.
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