RM0016 Serial peripheral interface (SPI)
Doc ID 14587 Rev 8 267/449
SPI communication using CRC is possible through the following procedure:
● Program the CPOL, CPHA, LSBfirst, BR, SSM, SSI and MSTR values.
● Program the polynomial in the SPI_CRCPR register
● Enable the CRC calculation by setting the CRCEN bit in the SPI_CR1 register. This
also clears the SPI_RXCRCR and SPI_TXCRCR registers
● Enable the SPI by setting the SPE bit in SPI_CR1
● Start the communication and sustain the communication until all but one byte has been
transmitted or received.
● On writing the last byte to the Txbuffer, set the CRCNext bit in the SPI_CR2 register to
indicate that after transmission of the last byte, the CRC should be transmitted. The
CRC calculation will be frozen during the CRC transmission.
● After transmitting the last byte, the SPI transmits the CRC. CRCNext bit is reset. The
CRC is also received and compared against the SPI_RXCRCR value. If the value does
not match, the CRCERR flag in SPI_SR is set and an interrupt can be generated when
the ERRIE in the SPI_ICR register is set.
Note: With high bit rate frequencies, the user must take care when transmitting CRC. As the
number of used CPU cycles has to be as low as possible in the CRC transfer phase, the
calling of software functions in the CRC transmission sequence is forbidden to avoid errors
in the last data and CRC reception.
20.3.7 Status flags
There are three status flags to allow the application to completely monitor the state of the
SPI bus.
Tx buffer empty flag (TXE)
When set, this flag indicates that the Tx buffer is empty and that the next data to be
transmitted can be loaded into the buffer. The TXE flag is reset when writing the SPI_DR
register.
Rx buffer not empty (RXNE)
When set, this flag indicates that there is a valid received data in the Rx buffer. This flag is
reset when SPI_DR is read.
Busy flag (BSY)
This BSY flag is set and reset by hardware (writing to this flag has no effect). The BSY flag
indicates the state of the communication layer of the SPI.
When BSY is set, it indicates that the SPI is busy communicating. There is one exception in
master mode / bidirectional receive mode (MSTR=1 and BDM=1 and BDOE=0) where the
BSY flag is kept low during the reception.
The BSY flag is useful to detect the end of a transfer if the software wants to disable the SPI
and enters Halt mode (or disable the peripheral clock). This will avoid corrupting the last
transfer. For this, the procedure described below must be strictly respected.
The BSY flag is also useful to avoid write collisions in a multimaster system.
The BSY flag is set when a transfer starts with the exception of master mode / bidirectional
receive mode (MSTR = 1 and BDM = 1 and BDOE = 0).
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