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RM0016 16-bit advanced control timer (TIM1)

Doc ID 14587 Rev 8 159/449

Using one timer to enable another timer

Example 1

The enable of timer B is controlled with the output compare 1 of timer A (refer to Figure 56

for connections). Timer B counts on the divided internal clock only when OC1REF of timer A

is high. Both counter clock frequencies are divided by four by the prescaler compared to

MASTER

CK_CNT

= f

MASTER

/4).

1. Configure timer A master mode to send its output compare 1 reference (OC1REF)

signal as trigger output (MMS = 100 in the TIMx_CR2 register).

2. Configure the timer A OC1REF waveform (TIMx_CCMR1 register)

3. Configure timer B to get the input trigger from timer A (TS = 001 in the TIMx_SMCR

4. Configure timer B in trigger gated mode (SMS = 101 in TIMx_SMCR register)

5. Enable timer B by writing 1 in the CEN bit (TIMx_CR1 register)

6. Start timer A by writing 1 in the CEN bit (TIMx_CR1 register)

Note: The counter 2 clock is not synchronized with counter 1. This mode only affects the timer B

counter enable signal.

Figure 56. Gating timer B with OC1REF of timer A

In Figure 56, the timer B counter and prescaler are not initialized before being started.

Therefore, they start counting from their current value. It is possible to start from a given

value by resetting both timers before starting timer A. In this case, any value can be written

in the timer counters. The timers can easily be reset by software using the UG bit in the

TIMx_EGR registers.

Timer B-TIF

Write TIF=0

FC FD FE FF 00

3045 3047 3048

MASTER

Timer A-OC1REF

Timer A-CNT

Timer B-CNT

3046

ST STM8S Reference Manual

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